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general description the max17009 is a 2-phase, step-down interleaved,fixed-frequency controller for amd? serial vid inter- face (svi) cpu core supplies. power-on detection ofthe cpu configures the max17009 as two independent single-phase regulators for a dual cpu core applica- tion, or one high-current, dual-phase, combined-output regulator for a unified core application. a reference buffer output (nbv_buf) sets the voltage-regulation level for a north bridge (nb) regulator, completing the total cpu cores and nb power requirements. the max17009 is fully amd svi compliant. output volt- ages are dynamically changed through a 2-wire serial interface, allowing the switching regulator and the refe- rence buffer to be individually programmed to different voltages. a programmable slew-rate controller enables controlled transitions between vid codes, soft-start limits the inrush current, and soft-shutdown brings the output voltage back down to zero without any negative ring. transient phase repeat improves the response of the fixed-frequency architecture. independently program- mable ac and dc droop and selectable offset improve stability and reduce the total output-capacitance requirement. a thermistor-based temperature sensor allows for a programmable thermal-fault output ( vrhot ). the max17009 includes thermal-fault protec- tion, undervoltage protection (uvp), and selectable out-put overvoltage protection (ovp). when any of these protection features detect a fault, the controller shuts down. true differential current sensing improves cur- rent limit, load-line accuracy, and current balance when operating in combined mode. the max17009 has an adjustable switching frequency, allowing 100khz to 1.2mhz per-phase operation. applications mobile amd svi core supplymultiphase cpu core supply voltage-positioned, step-down converters notebook/desktop computers features ? dual-output, fixed-frequency, core supplycontroller ? separate or combinable outputs detected atpower-up ? reference buffer output for nb controller ? ?.4% v out accuracy over line, load, and temperature ? amd svi-compliant serial interface ? 7-bit on-board dac: 0 to +1.550v output adjustrange ? dynamic phase selection optimizes active/sleepefficiency ? transient phase repeat reduces outputcapacitance ? true out-of-phase operation reduces inputcapacitance ? integrated boost switches ? programmable ac and dc droop ? programmable 100khz to 1.2mhz switchingfrequency ? accurate current balance and current limit ? adjustable slew-rate control ? power-good (pwrgd) and thermal-fault( vrhot ) outputs ? system power-ok (pgd_in) input ? drives large synchronous-rectifier mosfets ? 4v to 26v battery input-voltage range ? overvoltage, undervoltage, and thermal-faultprotection ? power sequencing and timing ? soft-startup and soft-shutdown ? < 1? typical shutdown current max17009 amd mobile serial vid dual-phase fixed-frequency controller ________________________________________________________________ maxim integrated products 1 ordering information 19-0814; rev 0; 5/07 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes a lead-free package. * ep = exposed pad. evaluation kit available part temp range pin-package pkg code MAX17009GTL+ -40c to +105c 40 tqfn-ep*, 5mm x 5mm t4055-1 pin configuration appears at end of data sheet. amd is a registered trademark of advanced micro devices, inc. downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics(circuit of figure 2, v in = 12v, v cc = v dd1 = v dd2 = shdn = pgd_in = 5v, v ddio = 1.8v, pro = option = gnds_nb = gnds_ = gnd_, fbdc_ = fbac_ = csp_ = csn_ = 1.2v, all dac codes set to the 1.2v code, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd1, v dd2, v cc , v ddio to gnd_............................-0.3v to +6v pwrgd to gnd_......................................................-0.3v to +6v fbdc_, fbac_, pro to gnd_ ...................-0.3v to (v cc + 0.3v) gnds2, thrm, vrhot to gnd_.............................-0.3v to +6v csp_, csn_, ilim to gnd_......................................-0.3v to +6v svc, svd, pgd_in to gnd_....................................-0.3v to +6v nbv_buf, nbskp to gnd_ .......................-0.3v to (v cc + 0.3v) ref, osc, time, option to gnd_ ..........-0.3v to (v cc + 0.3v) bst1, bst2 to gnd_..............................................-0.3v to +36v bst1 to v dd1 ..........................................................-0.3v to +30v bst2 to v dd2 ..........................................................-0.3v to +30v lx1 to bst1..............................................................-6v to +0.3v lx2 to bst2..............................................................-6v to +0.3v dh1 to lx1 .............................................-0.3v to (v bst1 + 0.3v) dh2 to lx2 .............................................-0.3v to (v bst2 + 0.3v) dl1 to gnd_.............................................-0.3v to (v dd1 + 0.3v) dl2 to gnd_.............................................-0.3v to (v dd2 + 0.3v) gnds1, gnds_nb to gnd_.................................-0.3v to +0.3v continuous power dissipation (t a = +70?) multilayer pcb (derate 35.7mw/? above +70?) .....2857mw single-layer pcb (derate 22.2mw/? ab ove +70?) ..1778mw operating temperature range .........................-40? to +105? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units input supplies v in drain of external high-side mosfet 4 26 v bias v cc , v dd1 , v dd2 4.5 5.5 input voltage range v ddio 1.0 2.7 v v cc undervoltage-lockout threshold v uvlo v cc rising 50mv typical hysteresis 4.10 4.25 4.45 v v cc power-on reset threshold v cc falling edge, typical hysteresis = 1.1v,faults cleared and dl_ forced high when v cc falls below this level 1.8 v v ddio undervoltage-lockout threshold v ddio rising 100mv typical hysteresis 0.7 0.8 0.9 v quiescent supply current (v cc )i cc skip mode, fbdc_ forced above theirregulation points 51 0m a quiescent supply currents(v dd1 , v dd2 ) i dd1 , i dd2 skip mode, fbdc_ forced above theirregulation points 0.01 1 a q ui escent s up p l y c ur r ent ( v d d i o ) i ddio 10 25 ? shutdown supply current (v cc ) shdn = gnd 0.01 1 a shutdown supply currents(v dd1 , v dd2 ) shdn = gnd 0.01 1 a shutdown supply current (v ddio ) shdn = gnd 0.01 1 a reference voltage v ref v cc = 4.5v to 5.5v, no ref load 1.986 2.000 2.014 v sourcing: i ref = 0 to 500? -2 -0.2 reference load regulation sinking: i ref = 0 to -100? 0.21 6.2 mv ref fault lockout voltage typical hysteresis = 85mv 1.84 v downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units main smps controllers dac codes from 0.8375v to 1.5500v -0.4 +0.4 % dac codes from 0.5000v to 0.8250v -4 +4 dc output-voltage accuracy(note 1) v out dac codes below 0.4875v -10 +10 mv dc load regulation either smps, pwm mode, droop disabled,zero to full load -0.1 % line-regulation error either smps, 4v < v in < 26v 0.03 %/v gnds_ input range v gnds_ separate mode -200 +200 mv gnds_ gain a gnds_ separate: ? v out _/ ? v gnds _ , -200mv v gnds _ +200mv; combined: ? v out / ? v gnds1, -200mv v gnds1 +200mv 0.95 1.00 1.05 v/v gnds_ input bias current i gnds _- 2 + 2 a combined-mode detectionthreshold gnds2, detection after refok, latched,cleared by cycling shdn 0.7 0.8 0.9 v fbdc_ input bias current i fbdc0 _ csp_ = csn_ -3 +3 ? r osc = 143k (f osc = 300khz nominal) -5 +5 switching-frequency accuracy f osc r osc = 35.7k (f osc = 1.2mhz nominal) to 432k (f osc = 99khz nominal) -7.5 +7.5 % maximum duty factor d max 90 92 % minimum on-time t onmin 175 ns 50 % smps1-to-smps2 phase shift smps2 starts after smps1 180 d eg r ees r time = 143k , sr = 6.25mv/? -10 +10 duringtransition r time = 35.7k to 357k , sr = 25mv/? to 2.5mv/? -15 +15 % time slew-rate accuracy startup and shutdown 1 mv/? current limit current-limit threshold tolerance v limit v csp _ - v csn _ = 0.05 x (v ref - v ilim ), (v ref - v ilm ) = 0.2v to 1.0v -3 +3 mv zero-crossing threshold v zx v gnd _ - v lx _, skip mode 3 mv idle mode threshold tolerance v idle v csp _ - v csn _, skip mode, 0.15 x v limit -1.5 +1.5 mv cs_ input-leakage current csp_ and csn_ -0.2 +0.2 a cs_ common-mode input range csp_ and csn_ 0 2 v phase-disable threshold csp2 3 v cc - 1 v cc -0.4 v electrical characteristics (continued)(circuit of figure 2, v in = 12v, v cc = v dd1 = v dd2 = shdn = pgd_in = 5v, v ddio = 1.8v, pro = option = gnds_nb = gnds_ = gnd_, fbdc_ = fbac_ = csp_ = csn_ = 1.2v, all dac codes set to the 1.2v code, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) idle mode is a trademark of maxim integrated products, inc. downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller 4 _______________________________________________________________________________________ electrical characteristics (continued)(circuit of figure 2, v in = 12v, v cc = v dd1 = v dd2 = shdn = pgd_in = 5v, v ddio = 1.8v, pro = option = gnds_nb = gnds_ = gnd_, fbdc_ = fbac_ = csp_ = csn_ = 1.2v, all dac codes set to the 1.2v code, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units droop and current balance dc droop amplifiertransconductance g m ( fbdc _ ) ? i fbdc _/( ? v cs _), v fbdc _ = v csn _ = 1.2v, v csp _ - v csn _ = -60mv to +60mv 0.97 1.00 1.03 ms dc droop and current-balanceamplifier offset i fbdc _/g m(fbdc _ ) -1.5 +1.5 mv ac droop and current-balanceamplifier transconductance g m ( fbac _ ) ? i fbac _/( ? v cs _), v fbac _ = v csn _ = 1.2v, v csp _ - v csn _ = -60mv to +60mv 0.97 1.00 1.03 ms ac droop and current-balanceamplifier offset i fbac _/g m(fbac _ ) -1.5 +1.5 mv no-load positive offset withoffset enabled offset enabled, option = ref or gnd 12.5 mv transient detection threshold measured at fbdc_ with respect to steady-state fbdc_ regulation voltage, 5mv hysteresis (typ), transient phase-repeat enabled, option = open or gnd -32 -18 mv nb buffer dac codes from 0.8375v to 1.5500v -0.4 +0.4 % dac codes from 0.5000v to 0.8250v -4 +4 nbv_buf output voltageaccuracy v nbv _ buf dac codes below 0.4875v to 0.0125v -10 +10 mv r time = 143k , i nbv _ buf = 7.0? -10 +10 nbv_buf short-circuit current (sets slew rate together with external capacitor c nbv _ buf ) dac code set to1.2v, v nbv _ buf = 0.4v and 2v r tim e = 35.7k to 357k , i n bv _ bu f = 28? to 2.8a -15 +15 % gnds_nb input range v gnds _ nb -200 +200 mv gnds_nb gain a gnds _ nb ? v nbv_buf / ? v gnds _ nb, -200mv v gnds _ nb +200mv 0.95 1.00 1.05 v/v gnds_nb input bias current i gnds _ nb -2 +2 ? fault detection normal operation 250 300 350 mv output not in regulationafter a downward vid transition 1.80 1.85 1.90 output overvoltage trip threshold v ovp_ measured atfbdc_, rising edge minimum ovp threshold 0.8 v output overvoltage fault- propagation delay t ovp fbdc_ forced 25mv above trip threshold 10 ? output undervoltage-protectiontrip threshold v uvp measured at fbdc_ with respect tounloaded output voltage -450 -400 -350 mv downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller _______________________________________________________________________________________ 5 electrical characteristics (continued)(circuit of figure 2, v in = 12v, v cc = v dd1 = v dd2 = shdn = pgd_in = 5v, v ddio = 1.8v, pro = option = gnds_nb = gnds_ = gnd_, fbdc_ = fbac_ = csp_ = csn_ = 1.2v, all dac codes set to the 1.2v code, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units output undervoltage fault- propagation delay t uvp fbdc_ forced 25mv below trip threshold 10 ? measured atfbdc_ with respect to unloaded output voltage lower threshold, falling edge (undervoltage) -350 -300 -250 pwrgd threshold 15mv hysteresis (typ) upper threshold, rising edge (overvoltage) +150 +200 +250 v pwrgd propagation delay t pwrgd _ fbdc_ forced 25mv outside the pwrgdtrip thresholds 10 ? pwrgd output low voltage i sink = 4ma 0.4 v pwrgd leakage current i pwrgd _ high state, pwrgd forced to 5.5v 1 a pwrgd startup delay andtransition blanking time t blank measured from the time when fbdc_reaches the target voltage based on the slew rate set by r time 20 ? vrhot trip threshold measured at thrm, with respect to v cc , falling edge, 115mv hysteresis (typ) 29.5 30 30.5 % vrhot delay t vrhot thrm forced 25mv below the vrhot trip threshold, falling edge 10 s vrhot output low voltage i sink = 4ma 0.4 v vrhot leakage current high state, vrhot forced to 5v 1 a thrm input leakage -100 +100 na thermal-shutdown threshold t shdn hysteresis = 15? 160 ? gate drivers high state (pullup) 0.9 2.0 dh_ gate-driver on-resistance r on ( dh _ ) bst_ - lx_ forcedto 5v low state (pulldown) 0.7 2.0 dl_, high state 0.7 2.0 dl_ gate-driver on-resistance r on ( dl _ ) dl_, low state 0.25 0.6 dh_ gate-driver source/sinkcurrent i dh _ dh_ forced to 2.5v, bst_ - lx_ forced to 5v 2.2 a dl_ gate-driver source current i dl _ ( source ) dl_ forced to 2.5v 2.7 a dl_ gate-driver sink current i dl _ ( sink ) dl_ forced to 2.5v 8 a t dh _ dl dh_ low to dl_ high 15 25 40 dead time t dl _ dh dl_ low to dh_ high 9 20 35 ns internal boost diode switch r on bst1 to v dd1 , bst2 to v dd2 ; measure with 10ma of current 10 20 downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller 6 _______________________________________________________________________________________ electrical characteristics (continued)(circuit of figure 2, v in = 12v, v cc = v dd1 = v dd2 = shdn = pgd_in = 5v, v ddio = 1.8v, pro = option = gnds_nb = gnds_ = gnd_, fbdc_ = fbac_ = csp_ = csn_ = 1.2v, all dac codes set to the 1.2v code, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units 2-wire svi bus logic interface svi logic input current svc, svd -1 +1 ? svi logic input threshold svc, svd, rising edge,hysteresis = 0.15v ddio 0.3 x v ddio 0.7 x v ddio v svc clock frequency f svc 3.4 mhz start condition hold time t hd , sta 160 ns repeated start conditionsetup time t su , sta 160 ns stop condition setup time t su , sto 160 ns data hold t hd , dat a master device must internally provide ahold time of at least 300ns for the sda signal (referred to the v il of sck signal) to bridge the undefined region of scl? fallingedge 70 ns data setup time t su , dat 10 ns svc low period t low 160 ns svc high period t high 60 ns svc/svd rise and fall time t r , t f measured from 10% to 90% of v ddio 40 ns pulse width of spike suppression input filters on svd and svc suppressnoise spikes less than 50ns 20 ns inputs and outputs shdn , pgd_in -1 +1 logic input current pro , option -3 +3 ? logic input threshold shdn , rising edge, hysteresis = 225mv 0.8 2.0 v high v cc - 0.4 open 3.15 3.85 ref 1.65 2.35 four-level input-logic levels option low 0.4 v high v cc - 0.4 open 3.15 3.85 tri-level input-logic levels pro low 0.4 v pgd_in logic input threshold pgd_in 0.3 x v ddio 0.7 x v ddio v low state, i sink = 3ma 0.4 nbskp logic output voltage high state, i source = 3ma v cc - 0.4 v downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller _______________________________________________________________________________________ 7 electrical characteristics(circuit of figure 2, v in = 12v, v cc = v dd1 = v dd2 = shdn = pgd_in = 5v, v ddio = 1.8v, pro = option = gnds_nb = gnds_ = gnd_, fbdc_ = fbac_ = csp_ = csn_ = 1.2v, all dac codes set to the 1.2v code, t a = -40? to +105? , unless otherwise noted.) (note 2) parameter symbol conditions min max units input supplies v in drain of external high-side mosfet 4 26 v bias v cc , v dd1 , v dd2 4.5 5.5 input voltage range v ddio 1.0 2.7 v v cc undervoltage-lockout threshold v uvlo v cc rising 50mv typical hysteresis 4.10 4.45 v v ddio undervoltage-lockout threshold v ddio rising 100mv typical hysteresis 0.8 0.9 v quiescent supply current (v cc )i cc skip mode, fbdc_ forced above theirregulation points 10 ma quiescent supply currents(v dd1 , v dd2 ) i dd1 , i dd2 skip mode, fbdc_ forced above theirregulation points, t a = -40? to +85? 1 a q ui escent s up p l y c ur r ent ( v d d i o ) i ddio 25 ? shutdown supply current (v cc ) shdn = gnd, t a = -40? to +85? 1 a shutdown supply currents(v dd1 , v dd2 ) shdn = gnd, t a = -40? to +85? 1 a shutdown supply current (v ddio )t a = -40? to +85? 1 a reference voltage v ref v cc = 4.5v to 5.5v, no ref load 1.98 2.02 v sourcing: i ref = 0 to 500? -2 reference load regulation sinking: i ref = 0 to -100? 6.2 mv main smps controllers dac codes from 0.8375v to 1.5500v -0.6 +0.6 % dac codes from 0.5000v to 0.8250v -6 +6 dc output-voltage accuracy(note 1) v out dac codes from 0.4875v to 0.0125v -15 +15 mv gnds_ input range v gnds_ separate mode -200 +200 mv gnds_ gain a gnds_ separate: ? v out _ / ? v gnds _ , -200mv v gnds _ +200mv, combined: ? v out / ? v gnds1, -200mv v gnds1 +200mv 0.95 1.05 v/v combined-mode detectionthreshold gnds2, detection after refok, latched,cleared by cycling shdn 0.7 0.9 v r osc = 143k (f osc = 300khz nominal) -7.5 +7.5 switching-frequency accuracy f osc r osc = 35.7k (f osc = 1.2mhz nominal) to 432k (f osc = 99khz nominal) -10 +10 % maximum duty factor dmax 90 % minimum on-time t onmin 185 ns r time = 143k , sr = 6.25mv/ s -10 +10 time slew-rate accuracy duringtransition r time = 35.7k to 357k , sr = 25mv/? to 2.5mv/? -15 +15 % downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller 8 _______________________________________________________________________________________ electrical characteristics (continued)(circuit of figure 2, v in = 12v, v cc = v dd1 = v dd2 = shdn = pgd_in = 5v, v ddio = 1.8v, pro = option = gnds_nb = gnds_ = gnd_, fbdc_ = fbac_ = csp_ = csn_ = 1.2v, all dac codes set to the 1.2v code, t a = -40? to +105? , unless otherwise noted.) (note 2) parameter symbol conditions min max units current limit current-limit threshold tolerance v limit v csp _ - v csn _ = 0.05 x (v ref - v ilim ), (v ref - v ilm ) = 0.2v to 1.0v -3 +3 mv idle mode threshold tolerance v idle v csp _ - v csn _, skip mode, 0.15 x v limit -1.5 +1.5 mv cs_ common-mode input range csp_ and csn_ 0 2 v phase disable threshold csp2 3 v cc - 0.4 v droop and current balance dc droop amplifiertransconductance g m ( fbdc _ ) ? i fbdc _ /( ? v cs _), v fbdc _ = v csn _ = 1.2v, v csp _ - v csn _ = -60mv to +60mv 0.97 1.03 ms dc droop amplifier offset i fbdc _ /g m(fbdc _ ) -1.5 +1.5 mv ac droop and current-balanceamplifier transconductance g m ( fbac _ ) ? i fbac _ /( ? v cs _), v fbac _ = v csn _ = 1.2v, v csp _ - v csn _ = -60mv to +60mv 0.97 1.03 ms ac droop and current-balanceamplifier offset i fbac _/g m(fbac _ ) -1.5 +1.5 mv transient-detection threshold measured at fbdc_ with respect tosteady-state fbdc_ regulation voltage, 5mv hysteresis (typ), transient phase repeat enabled, option = open or gnd -32 -18 mv nb buffer dac codes from 0.8375v to 1.5500v -0.6 +0.6 % dac codes from 0.5000v to 0.8250v -6 +6 nbv_buf output-voltageaccuracy v nbv _ buf dac codes from 0.4875v to 0.0125v -15 +15 mv r time = 143k , i nbv _ buf = 7.0? -10 +10 nbv_buf short-circuit current (sets slew rate together with external capacitor c nbv _ buf ) dac code set to1.2v, v nbv _ buf = 0.4v and 2v r ti m e = 35.7k to 357k , i n b v _ bu f = 28? to 2.8a -15 +15 % gnds_nb input range v gnds _ nb -200 +200 mv gnds_nb gain a gnds _ nb ? v nbv_buf / ? v gnds _ nb, -200mv v gnds _ nb +200mv 0.95 1.05 v/v downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller _______________________________________________________________________________________ 9 electrical characteristics (continued)(circuit of figure 2, v in = 12v, v cc = v dd1 = v dd2 = shdn = pgd_in = 5v, v ddio = 1.8v, pro = option = gnds_nb = gnds_ = gnd_, fbdc_ = fbac_ = csp_ = csn_ = 1.2v, all dac codes set to the 1.2v code, t a = -40? to +105? , unless otherwise noted.) (note 2) parameter symbol conditions min max units fault detection output overvoltage trip threshold v ovp_ measured at fbdc_,rising edge normal operation 250 350 mv output undervoltage-protectiontrip threshold v uvp measured at fbdc_ with respect tounloaded output voltage -450 -350 mv measured at fbdc_with respect to unloaded output voltage lower threshold,falling edge (undervoltage) -350 -250 pwrgd threshold 15mv hysteresis (typ) upper threshold,rising edge (overvoltage) +150 +250 v pwrgd output low voltage i sink = 4ma 0.4 v vrhot trip threshold measured at thrm, with respect to v cc , falling edge, 115mv hysteresis (typ) 29.5 30.5 % vrhot output low voltage i sink = 4ma 0.4 v gate drivers high state (pullup) 2.0 dh_ gate-driver on-resistance r on ( dh _ ) bst_ - lx_ forcedto 5v low state (pulldown) 2.0 dl_, high state 2.0 dl_ gate-driver on-resistance r on ( dl _ ) dl_, low state 0.6 t dh _ dl dh_ low to dl_ high 15 40 dead time t dl _ dh dl_ low to dh_ high 9 40 ns internal boost diode switch r on bst1 to v dd1 , bst2 to v dd2 , measured with 10ma of current 20 2-wire svi bus logic interface svi logic input threshold svc, svd, rising edge,hysteresis = 0.15 x v ddio 0.3 x v ddio 0.7 x v ddio v svc clock frequency f svc 3.4 mhz start condition hold time t hd , sta 160 ns repeated start conditionsetup time t su , sta 160 ns stop condition setup time t su , sto 160 ns data hold t hd , dat a m aster device must i nternal ly p rovid e a hold tim e of at l east 300ns for the sd a sig nal (r efer r ed to the v il of s ck sig nal ) to b ri dg e the und efi ned r eg ion of s cls fal li ng ed ge 70 ns data setup time t su , dat 10 ns svc low period t low 160 ns svc high period t high 60 ns svc/svd rise and fall time t r , t f measured from 10% to 90% of v ddio 40 ns downloaded from: http:///
note 1: when the inductor is in continuous conduction, the output voltage has a dc regulation level lower than the error comparator threshold by 50% of the ripple. in discontinuous conduction, the output voltage will have a dc regulation level higher thanthe error comparator threshold by 50% of the ripple. note 2: specifications to t a = -40? to +105? are guaranteed by design, not production tested. max17009 amd mobile serial vid dual-phase fixed-frequency controller 10 ______________________________________________________________________________________ electrical characteristics (continued)(circuit of figure 2, v in = 12v, v cc = v dd1 = v dd2 = shdn = pgd_in = 5v, v ddio = 1.8v, pro = option = gnds_nb = gnds_ = gnd_, fbdc_ = fbac_ = csp_ = csn_ = 1.2v, all dac codes set to the 1.2v code, t a = -40? to +105? , unless otherwise noted.) (note 2) parameter symbol conditions min max units inputs and outputs logic input threshold shdn , rising edge, hysteresis = 225mv 0.8 2.0 v high v cc - 0.4 v open 3.15 3.85 ref 1.65 2.35 four-level input logic levels option low 0.4 v high v cc - 0.4 open 3.15 3.85 tri-level input logic levels pro low 0.4 v pgd_in logic input threshold pgd_in 0.3 x v ddio 0.7 x v ddio v svd svc t sustp t sudat t hddat t clh t r t hdstt v ih v il t cll t f t bf figure 1. timing definitions used in the electrical characteristics downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller ______________________________________________________________________________________ 11 1-phase efficiency vs. load current (v out = 1.2125v) max17009 toc01 load current (a) efficiency (%) 10 1 65 70 75 80 85 90 95 100 60 0.1 100 v in = 7v v in = 12v v in = 20v 2-phase efficiency vs. load current (v out = 1.2125v) max17009 toc02 load current (a) efficiency (%) 10 65 70 75 80 85 90 95 100 60 0.1 100 v in = 7v v in = 12v v in = 20v 1-phase output voltage vs. load current (v out = 1.2125v, -1.2mv/a droop) max17009 toc03 load current (a) output voltage (v) 10 15 5 1.17 1.19 1.21 1.23 1.251.15 02 0 v in = 12v 1-phase output voltage vs. load current (v out = 1.2000v, no droop) max17009 toc04 load current (a) output voltage (v) 10 15 5 1.17 1.19 1.21 1.23 1.251.15 02 0 v in = 12v 1-phase efficiency vs. load current (v out = 0.8000v) max17009 toc05 load current (a) efficiency (%) 10 1 65 70 75 80 85 90 95 100 60 0.1 100 v in = 7v v in = 12v v in = 20v 2-phase efficiency vs. load current (v out = 0.8000v) max17009 toc06 load current (a) efficiency (%) 10 65 70 75 80 85 90 95 100 60 0.1 100 v in = 7v v in = 12v v in = 20v 1-phase output voltage vs. load current (v out = 0.8000v, -1.2mv/a droop) max17009 toc07 load current (a) output voltage (v) 10 15 5 0.75 0.76 0.77 0.78 0.79 0.80 0.81 0.82 0.83 0.840.74 02 0 v in = 12v 1-phase switching frequency vs. load current max17009 toc08 load current (a) switching frequency (khz) 10 1 150 200 250 300 350100 0.1 100 v in = 7v v in = 12v v in = 20v maximum inductor current vs. input voltage max17009 toc09 input voltage (v) inductor current (a) 15 20 10 2119 23 25 27 29 52 5 peak currentdc current v out = 1.2v typical operating characteristics (circuit of figure 2, v in = 12v, v dd = v cc = 5v, v ddio = 2.5v, t a = +25?, unless otherwise noted.) downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller 12 ______________________________________________________________________________________ maximum inductor current vs. temperature max17009 toc10 temperature (%) inductor current (a) 20 40 60 80 -20 0 2119 23 25 27 29 -40 peak currentdc current v in = 12v v out = 1.2v current balance vs. load current max17009 toc11 total load current (a) per-phase current (a) 20 30 40 10 50 10 15 20 0 i out1 i out2 v out = 1.2v no-load supply current vs. input voltage max17009 toc12 input voltage (v) supply current (ma) 15 20 25 10 0.1 0.01 1 10 5 i in i dd1 + i dd2 i cc v out = 1.2v reference voltage distribution max17009 toc13 reference voltage (mv) sample percentage (%) 2.000 2.003 2.005 1.998 2010 0 30 40 50 1.995 sample size = 150 smps output offset voltage distribution max17009 toc14 output offset voltage (mv) sample percentage (%) -1 1 3 5 -3 3020 10 0 40 6050 70 -5 sample size = 150 v out1 v out2 v dac1 = v dac2 = 1.200v nbv_buf offset voltage distribution max17009 toc15 offset voltage (mv) sample percentage (%) -1 1 3 5 -3 4020 0 60 80 -5 sample size = 150 v dac_nb = 1.200v fbdc transconductance distribution max17009 toc16 transconductance (ms) sample percentage (%) 2010 0 30 40 50 sample size = 150 fbdc1fbdc2 1.000 1.005 1.010 0.995 0.990 reference voltage vs. load current max17009 toc17 ref load current ( a) reference voltage (v) 40 60 80 100 20 1.9991.998 2.000 2.001 2.002 0 typical operating characteristics (continued) (circuit of figure 2, v in = 12v, v dd = v cc = 5v, v ddio = 2.5v, t a = +25?, unless otherwise noted.) startup waveforms (heavy load) max17009 toc18 200 s/div a. shdn, 5v/divb. i lx1 , 10a/div c. v out1 , 0.5v/div d. i lx2 , 10a/div v in = 12v, v boot = 0.8v, i load1 = i load2 = 12a 00 0 0 0 0 0 ab c d e f g e. v out2 , 0.5v/div f. pwrgd, 5v/divg. v nbv_buf , 0.5v/div downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller ______________________________________________________________________________________ 13 startup sequence waveforms max17009 toc19 400 s/div a. shdn, 5v/divb. v nbv_buf , 0.5v/div c. v out1 , 0.5v/div d. v out2 , 0.5v/div v in = 12v, v boot = 1.0v, i load1 = i load2 = 3a 00 0 0 0 0 0 ab c d e f gh e. pwrgd, 3.3v/divf. pgd_in, 3.3v/div g. svc, 2v/div h. svd, 2v/div shutdown waveforms max17009 toc20 200 s/div a. shdn, 5v/divb. dl1, 10v/div c. v out1 , 0.5v/div d. dl2, 10v/divv in = 12v, i load1 = i load2 = 3a 3.3v 5v 1.2v 5v 1.2v1.2v 3.3v 0 a b cd e f g e. v out2 , 0.5v/div f. v nbv_buf , 2v/div g. pwrgd, 5v/div 1-phase load transient (-1.2mv/a droop) max17009 toc21 20 s/div a. v out1 , 50mv/div b. i lx1 , 10a/div c. lx1, 10v/div v in = 12v i load1 = 3a to 15a to 3a 1.2v 15a 3a 12v 0 a b c 1-phase transient phase repeat (-1.2mv/a droop) max17009 toc22 2 s/div a. v out1 , 50mv/div b. i lx1 , 10a/div c. lx1, 10v/div v in = 12v i load1 = 3a to 15a to 3a 1.2v 15a 3a 12v 0 a b c 1-phase load transient (no droop) max17009 toc23 20 s/div a. v out1 , 50mv/div b. i lx1 , 10a/div c. lx1, 10v/div v in = 12v i load1 = 3a to 15a to 3a 1.2v 15a 3a 12v 0 a b c 1-phase transient phase repeat (no droop) max17009 toc24 2 s/div a. v out1 , 50mv/div b. i lx1 , 10a/div c. lx1, 10v/div v in = 12v i load1 = 3a to 15a to 3a 1.2v 15a 3a 12v 0 a b c typical operating characteristics (continued) (circuit of figure 2, v in = 12v, v dd = v cc = 5v, v ddio = 2.5v, t a = +25?, unless otherwise noted.) ______________________________________________________________________________________ 13 2-phase load transient (-1.2mv/a droop) max17009 toc25 20 s/div a. v out1 , 50mv/div b. i lx1 , 10a/div c. i lx2 , 10a/div v in = 12v i load = 6a to 30a to 6a 1.2v 15a 3a 15a 0 a b c 2-phase transient phase repeat (-1.2mv/a droop) max17009 toc26 2 s/div a. v out1 , 50mv/div b. i lx1 , 10a/div c. i lx2 , 10a/div v in = 12v i load = 6a to 30a to 6a 1.2v 15a 3a 15a 0 a b c downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller 14 ______________________________________________________________________________________ 1-phase output overload max17009 toc27 200 s/div a. pwrgd, 5v/divb. v out1 , 1v/div c. dl1, 10v/div d. v out2 , 1v/div e. dl2, 10v/divf. v nbv_buf , 1v/div v in = 12v, i load1 = 3a to 30a, i load2 = 3a 3.3v 5v 1.2a1.2v 5v 1.2v 0 a b cd e f 1-phase output overvoltage max17009 toc28 200 s/div a. pwrgd, 5v/divb. v out1 , 1v/div c. dl1, 10v/div d. v out2 , 1v/div e. dl2, 10v/divf. v nbv_buf , 1v/div v in = 12v, i load1 = 50ma, i load2 = 3a 3.3v 5v 1.2a1.2v 5v 1.2v 0 a b cd e f dynamic output-voltage transitions (light load) max17009 toc29 100 s/div a. v nbv_buf , 1v/div b. lx1, 20v/divc. v out1 , 0.5v/div d. lx2, 20v/div e. v out2 , 0.5v/div f. svc, 5v/divg. svd, 5v/div v in = 12v, v dacs = 1.3v to 0.6v to 1.3v, i load1 = i load2 = 3a 1.3v 12v12v 2.5v 1.3v1.3v 0.6v0.6v 0.6v 2.5v a b cd e f g dynamic output-voltage transitions (heavy load) max17009 toc30 100 s/div a. v nbv_buf , 1v/div b. lx1, 20v/divc. v out1 , 0.5v/div d. lx2, 20v/div e. v out2 , 0.5v/div f. svc, 5v/divg. svd, 5v/div v in = 12v, v dacs = 1.3v to 0.6v to 1.3v, i load1 = i load2 = 10a 1.3v 12v12v 2.5v 1.3v1.3v 0.6v0.6v 0.6v 2.5v a b cd e f g pgd_in falling transitions max17009 toc31 10 s/div a. v nbv_buf , 200mv/div b. v out1 , 200mv/div c. v out2 , 200v/div d. lx1, 20v/div e. lx2, 20v/divf. pgd_in, 5v/div g. pwrgd, 5v/div v in = 12v, v boot = 1.1v, v dac1 = 0.8v, v dac2 = 1.3v , v nbv_buf = 0.8v, i load1 = i load2 = 3a 1.1v1.1v 12v12v 2.5v 0.8v0.8v 1.3v 2.5v a b cd e f g 14 ______________________________________________________________________________________ typical operating characteristics (continued) (circuit of figure 2, v in = 12v, v dd = v cc = 5v, v ddio = 2.5v, t a = +25?, unless otherwise noted.) downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller ______________________________________________________________________________________ 15 ______________________________________________________________________________________ 15 pin description pin name function 1 pwrgd open-drain, power-good output. pwrgd indicates when both smpss are in regulation. pwrgd is forced high impedance whenever the slew-rate controller is activ e (output-voltage transitions). after output-voltage transitions, except during power -up and power-down, if fbdc_ is in regulation, then pwrgd is high impedance. during startup, pwrgd is held low an additional 20s after the max17009 r eaches the startup boot voltage set by the svc, svd pins. the max17009 stores the boot vid when pwrgd first goes high. the stored boot vid is cleared by rising shdn . pwrgd is forced low in shutdown. when in pulse-skipping mode, the upper pwrgd threshold comparator is blank ed during a lower vid transition. the upper pwrgd threshold comparator is reenabled once the output is in regu lation (figure 4). 2 nbv_buf north bridge buffered reference voltage. this output is connected to t he refin input of the nb controller (switcher or ldo) to set the nb regulator voltage. the nbv_buf output current is set by the time resistor. the nbv_buf current and the total output capacitance set the nbv_buf slew rate: i nbv_buf = (7a) x (143k / r time ) nbv_buf slew rate = i nbv_buf / c nbv_buf i nbv_buf is the same during startup, shutdown, and any vid transition. bypass to gnd with a 100pf minimum low-esr (ceramic) capacitor at the n bv_buf pin. 3 shdn shutdown control input. connect high (2v to v cc ) for normal operation. connect to gr ound to put the ic into its 1a max shutdown state. during startup, the smps output voltages and the nbv_buf voltage are ramped up to the vol tage set by the svc, svd inputs. the smpss start up and shut down at a fixed s lew rate of 1mv/s. svc svd boot voltage (v boot ) ( pro = v cc or gnd) boot voltage (v boot ) ( pro = open) 0 0 1.1 1.1 0 1 1.0 1.2 1 0 0.9 1.0 1 1 0.8 0.8 the max17009 stores the boot vid when pwrgd first goes high. the stor ed boot vid is cleared by rising shdn . 4 ref 2.0v reference output. bypass to gnd with a 1f maximum low-esr (cer amic) capacitor. ref sources up to 500a for external loads. loading ref degrades output a ccuracy, according to the ref load-regulation error. 5 ilim current-limit adjust input. the positive current-limit threshold voltage i s precisely 1/20 of the voltage between ref and ilim over a 0.2v to 1.0v range of v(ref, ilim). the i min minimum current-limit threshold voltage in skip mode is precisely 15% of the corresponding positive current- limit threshold voltage. 6 osc oscillator adjustment input. connect a resistor (r osc ) between osc and gnd to set the switching frequency (per phase): f osc = 300khz x 143k / r osc a 35.7k to 432k corresponds to switching frequencies of 1.2mhz to 100khz, respecti vely. switching-frequency selection is limited by the minimum on-t ime. see the switching frequency bullet in the smps design procedre section. downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller 16 ______________________________________________________________________________________ pin name function 7 time slew-rate adjustment pin. connect a resistor r time from time to gnd to set the internal slew rate: pwm slew rate = (6.25mv/?) x (143k / r time ) nbv_buf slew rate = (7?) x (143k / r time ) / c nbv_buf where r time is between 35.7k and 357k for corresponding slew rates between 25mv/? to 2.5mv/?, respectively, for the smpss, and nbv_buf currents between 28? and 2.8?, respectively, for the nbv_buf. this slew rate applies to both upward and downward vid transitions, and to the transition from boot mode to vid mode. downward vid transition slew rate can appear slower because the output transition is not forced by the smps. the smps slew rate for startup and shutdown is fixed at 1mv/?. the nbv_buf slew rate is the same during startup, shutdown, and normal vid transitions. 8 svc s er i al v id c l ock. d ur i ng the p ow er - up seq uence and i n d eb ug m od e, s v c i s the m s b of the 2- b i t v id d ac . 9 svd s er i al v id d ata. d ur i ng the p ow er - up seq uence and i n d eb ug m od e, s v d i s the ls b of the 2- b i t v id d ac . 10 thrm input of internal comparator. connect the output of a resistor- and thermistor-divider (between v cc and gnd) to thrm. select the components so the voltage at thrm falls below 1.5v (30% of v cc ) at the desired high temperature. 11 gnds2 smps2 remote ground-sense input. normally connected to gnd directly at the load. gnds2 internally connects to a transconductance amplifier that fine tunes the output voltage compensating for voltage drops from the regulator ground to the load ground. connect gnds2 above 0.9v combined-mode operation (unified core). when operating in combined mode, gnds1 is used as the remote ground-sense input. 12 fbdc2 output of the dc voltage-positioning transconductance amplifier for smps2. connect a resistor r fbdc2 between fbdc2 and the positive side of the feedback remote sense to set the dc steady-state droop based on the voltage-positioning gain requirement: r fbdc2 = r droopdc / (r sense2 x g m(fbdc2) ) where r droopdc is the desired voltage positioning slope and g m(fbdc2) = 1ms typ. r sense2 is the value of the current-sense resistor that is used to provide the (csp2, csn2) current-sense voltage. to disable the load-line, short fbdc2 to the positive remote-sense point. fbdc2 is high impedance in shutdown. 13 fbac2 output of the ac voltage-positioning transconductance amplifier for smps2. the resistance between this pin and the positive side of the remote-sensed output voltage sets the transient ac droop: r fbac2 = r droopac / (r sense2 x g m(fbac2) ) where r droopac is the transient (ac) voltage-positioning slope that provides an acceptable tradeoff between stability and load transient response, g m(fbac2) and r sense2 is the value of the current-sense resistor that is used to provide the (csp2, csn2) current-sense voltage. the maximum difference between transient (ac) droop and dc droop should not exceed ?0mv at the maximum allowed load current (dc droop is set at the fbdc2 pin). internally, v(fbdc2 - gnds2) goes to the internal voltage integrator (slow dc loop), whereas v(fbac2 - gnds2) goes to the error comparator (fast transient loop). fbac2 is high impedance in shutdown. note: the ac and dc droop cannot be different by more than ?mv/a. 14 v ddio cpu i/o voltage (1.8v or 1.5v). logic thresholds for svd and svc are relative to the voltage at v ddio . 15 gnds_nb north bridge feedback remote-sense input, negative side. normally connected to gnd directly at the load. gnds_nb internally connects to a transconductance amplifier that fine tunes the nbv_buf output voltage compensating for voltage drops from the regulator ground to the load ground. pin description (continued) downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller ______________________________________________________________________________________ 17 pin name function 16 csn2 negative current-sense input for smps2. connect to the negative side of the output current-sensing resistor or the filtering capacitor if the dc resistance of the output inductor is utilized for current sensing. 17 csp2 positive current-sense input for smps2. connect to the positive side of the output current-sensing resistor or the filtering capacitor if the dc resistance of the output inductor is utilized for current sensing. connect csp2 to v cc to disable smps2. this allows the max17009 to operate as a 1-phase regulator. 18 v cc controller supply voltage. connect to a 4.5v to 5.5v source. bypass to gnd with 1? minimum. a v cc uvlo event that occurs while the ic is functioning is latched, and can only be cleared by cycling v cc power or by toggling shdn . 19 nbskp north bridge skip push-pull control output. when nbskp is high, the nb switching regulator is set to forced-pwm mode. when nbskp is low, the nb switching regulator is set to pulse-skipping mode. the nbskp level is set through the serial interface during normal operation. nbskp is high in shutdown and during soft-shutdown. nbskp is high in startup until commanded otherwise. 20 dh2 smps2 high-side, gate-driver output. dh2 swings from lx2 to bst2. low in shutdown. 21 lx2 smps2 inductor connection. lx2 is the internal lower supply rail for the dh2 high-side gate driver. also used as an input to phase 2? zero-crossing comparator. 22 bst2 boost flying-capacitor connection for the dh2 high-side gate driver. an internal switch between v dd2 and bst2 charges the flying capacitor during the time the low-side fet is on. 23 v dd2 supply voltage input for the dl2 driver. v dd2 is also the supply voltage used to internally recharge the bst2 flying capacitor during the off-time of phase 2. connect v dd2 to the 4.5v to 5.5v system supply voltage. bypass v dd2 to gnd with a 1? or greater ceramic capacitor. 24 dl2 smps2 low-side gate-driver output. dl2 swings from gnd2 to v dd2 . dl2 is forced low in shutdown. dl2 is also forced high when an output overvoltage fault is detected. dl2 is forced low in skip mode after an inductor current zero crossing (gnd2 - lx2) is detected. 25 gnd2 power ground for smps2. ground connection for the dl2 driver. also used as an input to smps2? zero- crossing comparator. gnd1 and gnd2 are internally connected. 26 gnd1 power ground for smps1. ground connection for the dl1 driver. also used as an input to smps1? zero- crossing comparator. gnd1 and gnd2 are internally connected. 27 dl1 smps1 low-side, gate-driver output. dl1 swings from gnd1 to v dd1 . dl1 is forced low in shutdown. dl1 is also forced high when an output overvoltage fault is detected. dl1 is forced low in skip mode after an inductor current zero crossing (gnd1 - lx1) is detected. 28 v dd1 supply voltage input for the dl1 driver. v dd1 is also the supply voltage used to internally recharge the bst1 flying capacitor during the off-time of phase 1. connect v dd1 to the 4.5v to 5.5v system supply voltage. bypass v dd1 to gnd with a 1? or greater ceramic capacitor. 29 bst1 boost flying-capacitor connection for the dh1 high-side gate driver. an internal switch between v dd1 and bst1 charges the flying capacitor during the time the low-side fet is on. 30 lx1 smps1 inductor connection. lx1 is the internal lower supply rail for the dh1 high-side gate driver. also used as an input to phase 1? zero-crossing comparator. 31 dh1 smps1 high-side, gate-driver output. dh1 swings from lx1 to bst1. low in shutdown. 32 vrhot open-drain output of internal comparator. vrhot is pulled low when the voltage at thrm goes below 1.5v (30% of v cc ). vrhot is high impedance in shutdown. pin description (continued) downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller 18 ______________________________________________________________________________________ pin name function 33 pro protection disable. pro also sets the max17009 in debug mode. connect pro high to disable ovp protection. connect pro to gnd to enable ovp protection. when pro is floated, the max17009 disables the ovp protection and also enters deb ug mode (see the shdn pin description). when pgd_in is low in debug mode, the max17009 d ac voltages are set by the 2-bit boot vid. when pgd_in is high, the max17009 changes to serial vid mode. 34 csp1 positive current-sense input for smps1. connect to the positive side of the output current-sensing resistor or the filtering capacitor if the dc resistance of the output inductor is utilized for current sensing. 35 csn1 negative current-sense input for smps1. connect to the negative side of the outpu t current-sensing resistor or the filtering capacitor if the dc resistance of the output inductor is utilized for current sensing. 36 pgd_in system power-good input. indicates to the max17009 that the system is ready to enter serial vid mod e. pgd_in is low when shdn first goes high, the max17009 decodes the boot vid to determine the bo ot voltage. the boot vid can be changed dynamically while pgd_in remains low and pwrgd. the boot vid is stored after pwrgd goes high. pgd_in goes high after the max17009 reaches the boot voltage. this indicates that the svi block is active, and the max17009 starts to respond to the serial-interface command s. after pgd_in has gone high, if at anytime pgd_in should go low, t he max17009 regulates to the previously stored boot vid. 37 option four-level input to enable offset and transient-phase repeat option offset enabled transient-phase repeat enabled v cc 0 0 open 0 1 ref 1 0 gnd 1 1 when offset is enabled, the max17009 enables a fixed +12.5mv offset on eac h of the smps vid codes after pgd_in goes high. this configuration is intended for applicati ons that implement a load- line. an external resistor at fbdc_ sets the load-line. the offset can be disabled by setting the psi_l bit to zero through the serial interface. when offset is disabled, the intended application has no load-line, and the fbdc_ pins are directly connected to the remote-sense points. transient phase repeat allows the max17009 to reenable the current phase i n response to a load transient, even after that phase has finished its on-pulse. 38 fbac1 output of the ac voltage-positioning transconductance amplifier f or smps1. the resistance between this pin and the positive side of the remote-sensed output voltage s ets the transient ac droop: r fbac1 = r droopac / (r sense1 x g m(fbac1) ) where r droopac is the transient (ac) voltage-positioning slope that pro vides an acceptable tradeoff between stability and load-transient response, g m(fbac1) and r sense1 is the value of the current-sense resistor that is used to pro vide the (csp1, csn1) current-sense voltage. the maximum difference between transient (ac) droop and dc droo p should not exceed 80mv at the maximum allowed load current (dc droop is set at the fbdc2 pin). internally, v(fbdc1 - gnds1) goes to the internal voltage integrator (slow dc loop), whereas v(fbac1 - gnds1) goes to the error comparator (fast-transient loop). fbac1 is high impedance in shutdown. note: the ac and dc droop cannot be different by more than 3mv/a. pin description (continued) downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller ______________________________________________________________________________________ 19 pin name function 39 fbdc1 output of the dc voltage-positioning transconductance amplifier for s mps1. connect a resistor r fbdc1 between fbdc1 and the positive side of the feedback remote sense to s et the dc steady- state droop based on the voltage-positioning gain requirement: r fbdc1 = r droopdc / (r sense1 x g m(fbdc1) ) where r droopdc is the desired voltage-positioning slope and g m(fbdc1) = 1ms typ. r sense1 is the value of the current-sense resistor that is used to pro vide the (csp1, csn1) current-sense voltage. to disable the load-line, short fbdc2 to the positive remote-sense p oint. fbdc1 is high impedance in shutdown. 40 gnds1 smps1 remote ground-sense input. normally connected to gnd directly at the load. gnds1 internally connects to a transconductance amplifier that fine tunes the output voltage c ompensating for voltage drops from the regulator ground to the load ground. gnds1 is the remote ground-sense input in combined-mode operation. ep ep exposed pad. connect the exposed backside pad to gnd1 and gnd2. pin description (continued) component v in = 7v to 20v v out = 1.0v - 1.3v / 18a per phase v in = 4.5v to 14v v out_ = 1.0v - 1.3v / 18a per phase mode separate, 2-phase mobile (gnds2 not high) separate, 2-phase mobile (gnds2 not high) switching frequency 280khz (r osc = 154k ) 600khz (r osc = 71.5k ) c in_ , input capacitor (per phase) (2) 10f, 25v taiyo yuden tmk432bj106km (2) 10f, 16v taiyo yuden tmk432bj106km c out_ , output capacitor (per phase) (2) 470f, 2v, 6m , low-esr capacitor nec/tokin psgd0e477m6 or panasonic eefud0d471l6 (2) 330f, 2.5v, 6m , low-esr capacitor panasonic eefsd0d331xr n h_ high-side mosfet (1) fairchildsemi fdms8690 (1) international rectifier irf7811w n l_ low-side mosfet (2) vishay si7336adp (2) fairchildsemi fdms8660s d l_ schottky rectifier 3a, 40v schottky diode central semiconductor cmsh3-40 none l_ inductor 0.45h, 30a, 1.1m power inductor toko fdue1040d-r45m or nec/tokin mpc1040lr45 0.22h, 25a, 1m power inductor nec/tokin mpc0730lr20 table 1. component selection for standard applications table 1 shows the component selection for standard applications and table 2 lists component suppliers.note: mobile applications should be designed for separate mode operation. component selection dependent on amd cpu ac and dc specifications. downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller 20 ______________________________________________________________________________________ standard application circuits the max17009 standard application circuit (figure 2)generates two independent 18a outputs for amd mobile cpu applications. see table 1 for component selections. table 2 lists the component manufacturers. detailed description the max17009 consists of a dual-fixed-frequency pwmcontroller that generates the supply voltage for two inde- pendent cpu cores. a reference buffer output (nbv_buf) sets the regulation voltage for a separate nb regulator. the cpu cores can be configured as independent outputs, or as a combined output based on the gnds2 pin strap (gnds2 pulled to 1.5v - 1.8v, which are the respective voltages for ddr3 and ddr2). both smps outputs and the nb buffer can be pro- grammed to any voltage in the vid table (see table 4) using the svi. the cpu is the svi bus master, while the max17009 is the svi slave. voltage transitions are commanded by the cpu as a single-step command from one vid code to another. the max17009 slews the smps outputs at the slew rate programmed by the external r time resistor. for the nb buffer, the slew rate is set by the combination of r time and the total capaci- tance on the output of the buffer.by default, the max17009 smpss are always in pulse- skip mode. in separate mode, the psi_l bit does not change the mode of operation, but removes the +12.5mv offset, if enabled by the option pin. in com- bined mode, the psi_l bit removes the +12.5mv offset and switches from 2-phase to 1-phase operation. the nb_skp output always follows the state of psi_l for the nb regulator. +5v bias supply (v cc , v dd ) the max17009 requires an external 5v bias supply inaddition to the battery. typically, this 5v bias supply is the notebook? main 95%-efficient 5v system supply. keeping the bias supply external to the ic improves efficiency and eliminates the cost associated with the 5v linear regulator that would otherwise be needed to supply the pwm circuit and gate drivers. the 5v bias supply powers both the pwm controller and internal gate-drive power, so the maximum current drawn is: i bias = i cc + f sw q g = 10ma to 60ma (typ) where i cc is provided in the electrical characteristics table, and f sw q g (per phase) is the driver? supply cur- rent, as defined in the mosfet? data sheet. if the +5vbias supply is powered up prior to the battery supply, the enable signal ( shdn going from low to high) must be delayed until the battery voltage is present to ensurestartup. switching frequency (osc) connect a resistor (r osc ) between osc and gnd to set the switching frequency (per phase): f sw = 300khz x 143k / r osc a 35.7k to 432k corresponds to switching frequencies of 1.2mhz to 100khz, respectively. high-frequency(1.2mhz) operation optimizes the application for the smallest component size, trading off efficiency due to higher switching losses. this may be acceptable in ultra-portable devices where the load currents are lower and the controller is powered from a lower voltage sup- ply. low-frequency (100khz) operation offers the best overall efficiency at the expense of component size and board space. minimum on-time (t on(min) ) must also be taken into consideration. see the switching frequencybullet in the smps design procedure section. manufacturer website avx www.avxcorp.com bi technologies www.bitechnologies.com central semiconductor www.centralsemi.com fairchild semiconductor www.fairchildsemi.com international rectifier www.irf.com kemet www.kemet.com nec tokin www.nec-tokin.com panasonic www.panasonic.com manufacturer website pulse www.pulseeng.com renesas www.renesas.com sanyo www.secc.co.jp siliconix (vishay) www.vishay.com sumida www.sumida.com taiyo yuden www.t-yuden.com tdk www.component.tdk.com toko www.tokoam.com table 2. component suppliers downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller ______________________________________________________________________________________ 21 refin skip v core_nb agnd from max17009 nb control power groundanalog ground pwrgd +3.3v +5v lx1 dh1 bst1 dl1 v dd1 gnd1 r vcc 10 c vcc 2.2 f c ref 0.22 f r osc r time v cc v ddio ilim v in 4.5v to 28v r sense1 1m c out1 2 x 470 f 6m v core0 /18a l1 0.45 h csp1 r6 100k vr_hot lx2 dh2 bst2 dl2 gnd2 serial input svc svdpgd_in shdn option to nb regulator osctime ref ep c nbv_buf connect to system 1.8v v ddio supply connect to system pwrok signal v dd2 c7 1000pf csn1 csp1 csn2 csp2 pro 3-level option: v cc = disable ovp open = debug mode gnd = enable ovp option v cc open ref gnd 00 1 1 01 0 1 offset ph-rpt pwr agnd agnd agnd agnd 3 4 5 67 8 9 1 14 1716 18 2021 22 23 2425 26 30 29 28 27 37 36 { 3435 32 31 v cc fbdc1 core0 sense_h fbac1 agnd 39 38 enable fbdc2 fbac2 12 13 gnds1 40 gnds2 11 r7 100k max17009 r ilim2 r thrm r ntc r ilim1 pro 33 agnd agnd agnd csn1 nb_skp 19 nbv_buf 2 thrm 10 r5 10 gnds_nb 15 agnd c vdd1 1 f c bst1 0.22 f n h1 n l1 d l1 pwr c vdd2 1 f pwr c in1 pwr v in 4.5v to 28v r sense2 1m c out2 2 x 470 f 6m v core1 /18a l2 0.45 h csp2 pwr r fbac1 1.5k r fbdc1 1.1 r1 100 c14700pf c3 1000pf csn2 c bst2 0.22 f n h2 n l2 d l2 c in2 pwr r csp1 75 c csp1 2.2nf csp1 r csn1 10 c csn1 1nf csn1 agnd r csp2 75 c csp2 2.2nf csp2 r csn2 10 c csn2 1nf csn2 core1 sense_h agnd r fbac2 1.5k r fbdc2 1.1 r2 100 c24700pf c4 1000pf core0 sense_l agnd r3 100 c54700pf core1 sense_l agnd r4 100 c64700pf nb regulator figure 2. standard application circuit downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller 22 ______________________________________________________________________________________ interleaved multiphase operation the max17009 interleaves both phases?esulting in 180 out-of-phase operation that minimizes the input and output filtering requirements, reduces electromagnetic interference (emi), and improves efficiency. the high- side mosfets do not turn on simultaneously during nor- mal operation. the instantaneous input current is effectively reduced by the number of active phases, resulting in reduced input-voltage ripple, esr power loss, and rms ripple current (see the input-capacitor selection section). therefore, the controller achieves high performance while minimizing the component count,which reduces cost, saves board space, and lowers component power requirements, making the max17009 ideal for high-power, cost-sensitive applications. transient-phase repeat when a transient occurs, the output-voltage deviationdepends on the controller? ability to quickly detect the transient and slew the inductor current. a fixed-fre- quency controller typically responds only when a clock edge occurs, resulting in a delayed transient response. to minimize this delay time, the max17009 includes enhanced transient detection and transient- phase- repeat capabilities. if the controller detects that the out- put voltage has dropped by 25mv, the transient- detection comparator immediately retriggers the phase that completed its on-time last. the controller triggers the subsequent phases as normal on the appropriate oscillator edges. this effectively triggers a phase a full cycle early, increasing the total inductor-current slew rate and providing an immediate transient response. the option pin setting enables or disables the tran- sient phase-repeat feature. keep option open or connected to gnd to enable transient-phase repeat. connect option to v cc or ref to disable transient- phase repeat. see the offset and transient-phase repeat (option) section. feedback adjustment amplifiers steady-state voltage-positioning amplifier (dc droop) each of the max17009 smps controllers includes twotransconductance amplifiers?ne for steady-state dc droop, and another for ac droop. the amplifiers?inputs are generated by summing their respective current-sense inputs, which differentially sense the voltage across either current-sense resistors or the inductor? dcr. the dc droop amplifier? output (fbdc) connects to the remote-sense point of the output through a resistor that sets each phase? dc voltage-positioning gain: where the target voltage (v target ) is defined in the nominal output-voltage selection section, and the fbdc amplifier? output current (i fbdc ) is determined by each phase? current-sense voltage:where v cs = v csp - v csn is the differential current- sense voltage, and g m(fbdc) is typically 1ms as defined in the electrical characteristics table. dc droop is typically used together with the +12.5mvoffset feature to keep within the dc tolerance window of the application. see the offset and transient-phase repeat ( option) section. the ripple voltage on fbdc must be less than the 18mv (min) transient phaserepeat threshold: where ? i l is the inductor ripple current, r esr is the effective output esr at the remote sense point, r sense is the current-sense element, and g m(fbdc) is 1.03ms (max) as defined in the electrical characteristics table. the worst-case inductor ripple occurs at the maximuminput voltage and the minimum output-voltage conditions: to disable voltage positioning, set r fbdc to zero. transient voltage-positioning amplifier (ac droop) the ac droop amplifier? output (fbac) connects tothe remote-sense point of the output through a resistor that sets each phase? ac voltage-positioning gain: where the target voltage (v target ) is defined in the nominal output-voltage selection section, and the fbac amplifier? output current (i fbac ) is determined by each phase? current-sense voltage:where v cs = v csp - v csn is the differential current- sense voltage, and g m(fbac) is 1.03ms (max), as defined in the electrical characteristics table. ac droop is required for stable operation of themax17009. a minimum of 1mv/a is recommended. ac droop must not be disabled. ig v fbac m fbac cs = () vv ri out target fbac fbac = i vvv vfl l max out min in max out min in max osc () () ( ) () () = () r mv i rrg fbdc l esr sense m fbdc ? ? ? ? ? ? 18 () ? ir g r ir mv l sense m fbdc fbdc l esr () + 18 ig v fbdc m fbdc cs = () vv ri out target fbdc fbdc = downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller ______________________________________________________________________________________ 23 the maximum allowable ac droop is limited by the rec-ommended integrator correction range of ?00mv and on the dc droop: differential remote sense the max17009 controller includes independent differ-ential, remote-sense inputs for each cpu core to elimi- nate the effects of voltage drops along the pc board (pcb) traces and through the processor? power pins. the feedback-sense (fbdc_) input connects to the voltage-positioning resistor (r fbdc_ ). the ground- sense (gnds_) input connects to an amplifier thatadds an offset directly to the target voltage, effectively adjusting the output voltage to counteract the voltage drop in the ground path. connect the feedback-sense (fbdc_) voltage-positioning resistor (r fbdc_ ), and ground-sense (gnds_) input directly to the respectivecpu core? remote-sense outputs as shown in figure 2. gnds2 has a dual function. at power-on, the voltage level on gnds2 configures the max17009 as two inde- pendent switching regulators, or one higher current two-phase regulator. keep gnds2 low during power- up to configure the max17009 in separate mode. connect gnds2 to a voltage above 0.8v (typ) for com- bined-mode operation. in the amd mobile system, this is automatically done by the cpu that is plugged into the socket that pulls gnds2 to the v ddio voltage level. the max17009 checks the gnds2 level at the timewhen the internal refok signal goes high, and latches the operating mode information (separate or combined mode). this latch is cleared by cycling the shdn pin. integrator amplifier an internal integrator amplifier forces the dc averageof the fbdc_ voltage to equal the target voltage. this transconductance amplifier integrates the feedback voltage and provides a fine adjustment to the regulation voltage (figure 3), allowing accurate dc output-voltage regulation regardless of the output-ripple voltage. the integrator amplifier has the ability to shift the output voltage by ?00mv (min). the max17009 disables the integrator by connecting the amplifier inputs together at the beginning of all vid transitions done in pulse-skipping mode. the integrator remains disabled until 20? after the transition is com- pleted (the internal target settles), and the output is in regulation (edge detected on the error comparator). when voltage positioning is disabled (r fbdc_ = 0 ), the ac droop setting must be less than the ?00mv minimum adjustment range of the integrator amplifier toguarantee proper dc output-voltage accuracy. see the steady state voltage-positioning amplifiers (dc droop) and the transient voltage-positioning amplifiers (ac droop) sections. 2-wire serial interface (svc, svd) the max17009 supports the 2-wire, write only, serial-interface bus as defined by the amd serial vid interface specification. the serial interface is similar to the high-speed 3.4mhz i 2 c bus, but without the master mode sequence. the bus consists of a clock line (svc)and a data line (svd). the cpu is the bus master, and the max17009 is the slave. the max17009 serial inter- face works from 100khz to 3.4mhz. in the amd mobile application, the bus runs at 3.4mhz. the serial interface is active only after pgd_in goes high in the startup sequence. the cpu sets the vid voltage of the three internal dacs and the psi_l bit through the serial interface. during the startup sequence, the svc and svd inputs serve an alternate function to set the 2-bit boot vid for all three dacs while pwrgd is low. in debug mode, the svc and svd inputs function in the 2-bit vid mode when pgd_in is low, and in the serial-interface mode when pgd_in is high. nominal output-voltage selection smps output voltage the nominal no-load output voltage (v target_ ) for each smps is defined by the selected voltage refer-ence (vid dac) plus the remote ground-sense adjust- ment (v gnds ) and the offset voltage (v offset ) as defined in the following equation:where v dac is the selected vid voltage of the smps dac, v gnds is the ground-sense correction voltage, and v offset is the +12.5mv offset enabled by the option pin, when the psi_l is set high. nbv_buf output voltage the nominal output voltage (v target ) for the nbv_buf is defined by the selected voltage reference (vid dac)plus the remote ground-sense adjustment (v gnds ), as defined in the following equation:where v dac_ is the selected vid voltage of the nbv_buf dac, and v gnds_nb_ is the ground-sense correction voltage. the offset voltage (v offset ) is not applied to nbv_buf. vv vv target nbv buf dac gnds nb == + __ vvvvv target fbdc dac gnds offset ==+ + rr mv msi r fbac fbdc load max sense 100 103 . () downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller 24 ______________________________________________________________________________________ dac1 pwrgd uvlo refok run ref nbskp v cc ref (2.0v) debugmode nbv_buf svc svd svi interface pgd_in shdn v ddio 7-bit vidskip1 dac2 7-bit vidskip2 dac3 7-bit vid osc oscillator pwm_ gnds1 run fault2 fault1 time pro pro dacout1 time blank1 target1 blank2 target2 dacout2 v ddio dacout3 clock2 gnds2 bst_ dh_ lx_ gnd_ dl_ v dd phase 1 target and slew-rate block combine skip3 gnds1 ofs_en 0.8v clock1 i slope1 i slope2 x2 ab a/b out gnds_nb vrhot thrm driver block csp_ csn_ fbdc_ pwm block fbac_ x2 pwm_ clock_ target_ imin_ imax_ skip_ tpr_en i slope_ drp_en csa_ option 4-level decode tpr_en ofs_en ilim current limit x2 imax_ ineg_ imin_ csa_ ref skip_ skip_ ccv1s ccv1 ccv2 ccv2s ccv_s ccv_ phase 2 fault block phase 1 fault block fault2 fbdc2 target2 pgd1 fault1 fbdc1 target1 pgd2 blank2 blank1 3-level decode debugmode max17009 0.3 x v cc phase 2 target and slew-rate block figure 3. functional diagram downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller ______________________________________________________________________________________ 25 7-bit dac inside the max17009 are three 7-bit digital-to-analogconverters (dacs). each dac can be individually pro- grammed to different voltage levels through the serial- interface bus. the dac sets the target for the output voltage for the smpss and the nb buffer output (nbv_buf). the available dac codes and resulting output voltages are compatible with the amd svi (table 4) specifications boot voltage on startup, the max17009 slews the target for all threedacs from ground to the boot voltage set by the svc and svd pin voltage levels. while the output is still below regulation, the svc and svd levels can be changed, and the max17009 sets the dacs to the new boot volt- age. once the programmed boot voltage is reached and pwrgd goes high, the max17009 stores the boot vid. changes in the svc and svd settings do not change the output voltage once the boot vid is stored. when pgd_in goes high, the max17009 exits boot mode, and the three dacs can be independently set to any voltage in the vid table through the serial interface. if pgd_in goes from high to low anytime after the boot vid is stored, the max17009 sets all three dacs back to the voltage of the stored boot vid. when in debug mode ( pro = open), the max17009 uses a different boot-voltage code set. keepingpgd_in low allows the svc and svd inputs to set the three dacs to different voltages in the boot-voltage code table. when pgd_in is subsequently set high, the three dacs can be independently set to any voltage in the vid table serial interface. table 3 shows the boot- voltage code table. offset a +12.5mv offset can be added to both smps dacvoltages for applications that include dc droop. the offset is applied only after the max17009 exits boot mode (pgd_in going from low to high), and the max17009 enters the serial-interface mode. the offset is disabled when the psi_l bit is set, saving more power when the load is light. the option pin setting enables or disables the+12.5mv offset. connect option to ref or gnd to enable the offset. keep option open or connected to v cc to disable the offset. see the offset and transient- phase repeat ( option) section. output-voltage transition timing smps output-voltage transition the max17009 performs positive voltage transitions in acontrolled manner, automatically minimizing input surge currents. this feature allows the circuit designer to achieve nearly ideal transitions, guaranteeing just-in-time arrival at the new output voltage level with the lowest possible peak currents for a given output capacitance. the slew rate (set by resistor r time ) must be set fast enough to ensure that 35.7k and 357k for corre- sponding slew rates between 25mv/? to 2.5mv/?,respectively, for the smpss. at the beginning of an output-voltage transition, the max17009 blanks both pwrgd comparator thresh- olds, preventing the pwrgd open-drain output from changing states during the transition. at the end of an upward vid transition, the controller enables both pwrgd thresholds approximately 20? after the slew- rate controller reaches the target output voltage. at the end of a downward vid transition, the upper pwrgd threshold is enabled only after the output reaches the lower vid code setting. the max17009 automatically controls the current to the minimum level required to complete the transition in the calculated time. the slew-rate controller uses an internal capacitor and current source programmed by r time to transition the output voltage. the total transition timedepends on r time , the voltage difference, and the accuracy of the slew-rate controller (c slew accuracy). the slew rate is not dependent on the total outputcapacitance, as long as the surge current is less than the current limit set by ilim. for all dynamic positive vid transitions, the transition time (t tran ) is given by: where dv target /dt = 6.25mv/? x 143k / r time is the slew rate, v old is the original output voltage, and v new is the new target voltage. see the time slew-rateaccuracy row in the electrical characteristics table for slew-rate limits.the output voltage tracks the slewed target voltage, making the transitions relatively smooth. the average inductor current per phase required to make an output- voltage transition is: t vv dv dt tran new old target = () / svc svd boot voltage (v boot ) ( pro = v c c o r g n d ) boot voltage (v boot ) ( pro = open) 0 0 1.1 1.4 0 1 1.0 1.2 1 0 0.9 1.0 1 1 0.8 0.8 table 3. boot-voltage code table downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller 26 ______________________________________________________________________________________ where dv target /dt is the required slew rate, c out is the total output capacitance.the max17009 smpss remain in a pulse-skipping mode even during upward and downward vid transi- tions. as such, downward vid transitions are not forced, and the output voltage may take a longer time to settle to the lower vid code. the discharge rate of the output voltage during downward transitions is dependent on the load current and total output capaci- tance for loads less than a minimum current, and dependent on the r time programmed slew rate for heavier loads. the critical load current (i load(crit) ) where the transition time is dependent on the load is:for load currents less than i load(crit) , the transition time is:for soft-start and shutdown, the controller uses a fixed slew rate of 1mv/?. figure 4 is the vid transition timing diagram. table 4 shows the output-voltage vid dac codes. t cd v i trans out target load ? i c dv dt load crit out target () / ? () i c dv dt l out target ? () / core voltage (core target) pwrgd core load light load heavy load svc/svd bus idle bus idle bus idle pwrgd upper threshold pwrgd lower threshold 20 s2 0 s core target upper threshold blanked 20 s blank high impedance blank high impedance blank high impedance figure 4. vid transition timing figure svid[6:0] output voltage (v) svid[6:0] output voltage (v) svid[6:0] output voltage (v) svid[6:0] output voltage (v) 000_0000 1.5500 010_0000 1.1500 100_0000 0.7500 110_0000 0.3500 000_0001 1.5375 010_0001 1.1375 100_0001 0.7375 110_0001 0.3375 000_0010 1.5250 010_0010 1.1250 100_0010 0.7250 110_0010 0.3250 000_0011 1.5125 010_0011 1.1125 100_0011 0.7125 110_0011 0.3125 000_0100 1.5000 010_0100 1.1000 100_0100 0.7000 110_0100 0.3000 000_0101 1.4875 010_0101 1.0875 100_0101 0.6875 110_0101 0.2875 000_0110 1.4750 010_0110 1.0750 100_0110 0.6750 110_0110 0.2750 000_0111 1.4625 010_0111 1.0625 100_0111 0.6625 110_0111 0.2625 000_1000 1.4500 010_1000 1.0500 100_1000 0.6500 110_1000 0.2500 000_1001 1.4375 010_1001 1.0375 100_1001 0.6375 110_1001 0.2375 table 4. output voltage vid dac codes downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller ______________________________________________________________________________________ 27 nbv_buf output-voltage transition the max17009 includes a buffered output voltage thatsets the target for the nb regulator. when a voltage transition on the nb dac occurs, the nbv_buf sources or sinks a programmed current on its output. the programmed current (i nbv_buf ) is set by r time . r time is between 35.7k and 357k for corresponding i nbv_buf between 28? and 2.8?, respectively: i nbv_buf = (7?) x (143k / r time ) i nbv_buf and the external capacitor (c nbv_buf ) set the voltage slew rate of the nbv_buf: dv nbv_buf /dt = i nbv_buf / c nbv_buf program the nb regulator with a slew rate faster thanthat set by nbv_buf to allow the nbv_buf to control the nb regulator? output slew rate. alternatively, the nb regulator can be programmed with the desired slew rate, and the nbv_buf voltage can approach a step function by keeping c nbv_buf small. a minimum of 100pf capacitor is required. pulse-skipping operation the smps of the max17009 always operates in pulse-skipping mode. pulse-skipping mode enables the driver? zero-crossing comparator, so the driver pulls its dl low when ?ero?inductor current is detected (v gnd - v lx = 0). this keeps the inductor from discharging the outputcapacitors and forces the controller to skip pulses under light-load conditions to avoid overcharging the output. in the pulse-skipping operation, the controller termi- nates the on-time when the output voltage exceeds the feedback threshold and when the current-sense voltage exceeds the idle mode current-sense threshold (v idle = 0.15 x v limit ). under heavy-load conditions, the con- tinuous inductor current remains above the idle modecurrent-sense threshold, so the on-time depends only on the feedback-voltage threshold. under light-load conditions, the controller remains above the feedback voltage threshold, so the on-time duration depends solely on the idle mode current-sense threshold, which is approximately 15% of the full-load peak current-limit threshold set by ilim. svid[6:0] output voltage (v) svid[6:0] output voltage (v) svid[6:0] output voltage (v) svid[6:0] output voltage (v) 000_1010 1.4250 010_1010 1.0250 100_1010 0.6250 110_1010 0.2250 000_1011 1.4125 010_1011 1.0125 100_1011 0.6125 110_1011 0.2125 000_1100 1.4000 010_1100 1.0000 100_1100 0.6000 110_1100 0.2000 000_1101 1.3875 010_1101 0.9875 100_1101 0.5875 110_1101 0.1875 000_1110 1.3750 010_1110 0.9750 100_1110 0.5750 110_1110 0.1750 000_1111 1.3625 010_1111 0.9625 100_1111 0.5625 110_1111 0.1625 001_0000 1.3500 011_0000 0.9500 101_0000 0.5500 111_0000 0.1500 001_0001 1.3375 011_0001 0.9375 101_0001 0.5375 111_0001 0.1375 001_0010 1.3250 011_0010 0.9250 101_0010 0.5250 111_0010 0.1250 001_0011 1.3125 011_0011 0.9125 101_0011 0.5125 111_0011 0.1125 001_0100 1.3000 011_0100 0.9000 101_0100 0.5000 111_0100 0.1000 001_0101 1.2875 011_0101 0.8875 101_0101 0.4875 111_0101 0.0875 001_0110 1.2750 011_0110 0.8750 101_0110 0.4750 111_0110 0.0750 001_0111 1.2625 011_0111 0.8625 101_0111 0.4625 111_0111 0.0625 001_1000 1.2500 011_1000 0.8500 101_1000 0.4500 111_1000 0.0500 001_1001 1.2375 011_1001 0.8375 101_1001 0.4375 111_1001 0.0375 001_1010 1.2250 011_1010 0.8250 101_1010 0.4250 111_1010 0.0250 001_1011 1.2125 011_1011 0.8125 101_1011 0.4125 111_1011 0.0125 001_1100 1.2000 011_1100 0.8000 101_1100 0.4000 111_1100 0 001_1101 1.1875 011_1101 0.7875 101_1101 0.3875 111_1101 0 001_1110 1.1750 011_1110 0.7750 101_1110 0.3750 111_1110 0 001_1111 1.1625 011_1111 0.7625 101_1111 0.3625 111_1111 0 table 4. output voltage vid dac codes (continued) downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller 28 ______________________________________________________________________________________ during downward vid transitions, the controller tem-porarily sets the ovp threshold to 1.85v (typ), preventing false ovp faults. once the error amplifier detects that the output voltage is in regulation, the ovp threshold tracks the selected vid dac code. the max17009 automati- cally uses forced-pwm operation during soft-shutdown. when configured for separate-mode operation, both smpss remain in pulse-skipping mode, regardless of the psi_l bit state. when configured for combined-mode operation, the psi_l bit sets the max17009 in 1-phase pulse-skipping mode or 2-phase pulse-skipping mode. idle mode current-sense threshold the idle mode current-sense threshold forces a lightlyloaded regulator to source a minimum amount of power with each on-time since the controller cannot terminate the on-time until the current-sense voltage exceeds the idle mode current-sense threshold (v idle = 0.15 x v limit ). since the zero-crossing comparator prevents the switching regulator from sinking current, the con-troller must skip pulses to avoid overcharging the out- put. when the clock edge occurs, if the output voltage still exceeds the feedback threshold, the controller does not initiate another on-time. this forces the con- troller to actually regulate the valley of the output volt- age ripple under light-load conditions. automatic pulse-skipping crossover in skip mode, the max17009 zero-crossing compara-tors are active. therefore, an inherent automatic switchover to pfm takes place at light loads, resulting in a highly efficient operating mode. this switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current? zero crossing. the driver? zero-crossing comparator senses the inductor current across the low-side mosfet. once v gnd - v lx drops below the zero-crossing threshold, the driver forces dl low. this mechanism causes thethreshold between pulse-skipping pfm and nonskip- ping pwm operation to coincide with the boundary between continuous and discontinuous inductor-cur- rent operation (also known as the ?ritical-conduction point). the load-current level at which the pfm/pwm crossover occurs, i load(skip) , is given by: the switching waveforms may appear noisy and asyn-chronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. trade-offs in pfm noise vs. light-load efficiency are made by varying the inductor value. generally, low inductor values producea broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output-voltage ripple. penalties for using higher inductor values include larger physical size and degraded load-tran- sient response (especially at low input-voltage levels). current sense the output current of each phase is sensed differentially.a low offset voltage and high gain (10v/v) differential current amplifier at each phase allows low-resistance current-sense resistors to be used to minimize power dissipation. sensing the current at the output of each phase offers advantages, including less noise sensitivi- ty, more accurate current sharing between phases, and the flexibility of using either a current-sense resistor or the dc resistance of the output inductor. using the dc resistance (r dcr ) of the output inductor allows higher efficiency. in this configuration, the initialtolerance and temperature coefficient of the inductor? dcr must be accounted for in the output-voltage droop-error budget and power monitor. this current- sense method uses an rc filtering network to extract the current information from the output inductor (see figure 5). the time constant of the rc network should match the inductor? time constant (l/r dcr ): where c sense and r eq are the time-constant matching components. to minimize the current-sense error dueto the current-sense inputs?bias current (i csp and i csn ), choose r eq less than 2k and use the above equation to determine the sense capacitance(c sense ). choose capacitors with 5% tolerance and resistors with 1% tolerance specifications. temperaturecompensation is recommended for this current-sense method. see the voltage-positioning and loop compensation section for detailed information. when using a current-sense resistor for accurate output-voltage positioning, the circuit requires a differential rc filter to eliminate the ac voltage step caused by the equivalent series inductance (l esl ) of the current-sense resistor (see figure 5). the esl-induced voltage stepdoes not affect the average current-sense voltage, but results in a significant peak current-sense voltage error that results in unwanted offsets in the regulation voltage and results in early current-limit detection. similar to the inductor dcr sensing method above, the rc filter? time constant should match the l/r time constant formed by the current-sense resistor? parasitic inductance: l r rc dcr eq sense = i vvv vf l load skip out in out in sw () = () 2 downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller ______________________________________________________________________________________ 29 where l esl is the equivalent series inductance of the current-sense resistor, r sense is current-sense resis- tance value, and c sense and r eq are the time-con- stant matching components. combined-mode current balance when configured in combined mode, the max17009current-mode architecture automatically forces the individual phases to remain current balanced. smps1 is the main voltage-control loop, and smps2 maintains the current balance between the phases. this controlscheme regulates the peak inductor current of each phase, forcing them to remain properly balanced. therefore, the average inductor current variation depends mainly on the variation in the current-sense ele- ment and inductance value. peak current limit the max17009 current-limit circuit employs a fast peakinductor current-sensing algorithm. once the current- sense signal (csp to csn) of the active phase exceeds the peak current-limit threshold, the pwm controller ter- minates the on-time. see the peak-inductor current limit section in the smps design procedure section. l r rc esl sense eq sense = a) series sense-resistor sensing dh_ input (v in ) dl_ lx_ gnd c in n l n h d l csp_ csn_ l b) output inductor dcr sensing dh_ input (v in ) dl_ lx_ gnd c in n l n h d l csp_ csn_ c out inductor r1 c sense l esl r dcr sense resistor esl r sense c out r eq c sense r2 ( ) r dcr r1 + r2 r2 r eq = 1 1 r1 r2 c sense l r dcr = [ + ] for thermal compensation: r2 should consist of an ntc resistor in series with a standard thin-film resistor. max17009 max17009 figure 5. current-sense configurations downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller 30 ______________________________________________________________________________________ power-up sequence (por, uvlo, pgd_in) power-on reset (por) occurs when v cc rises above approximately 2v, resetting the fault latch and prepar-ing the controller for operation. the v cc undervoltage lockout (uvlo) circuitry inhibits switching until v cc rises above 4.25v. the controller powers up the refer-ence once the system enables the controller? cc above 4.25v and shdn driven high. with the reference in regulation, the controller ramps the smps andnbv_buf voltages to the boot voltage set by the svc and svd inputs: the soft-start circuitry does not use a variable current limit, so full output current is available immediately. pwrgd becomes high impedance approximately 20? after the smps outputs reach regulation. the boot vid isstored the first time pwrgd goes high. the max17009 is in pulse-skipping mode during soft-start, and in forced-pwm mode soft-shutdown. the nb regulator soft-start time is set by the nb regula- tor soft-start timer, or by t (nbv_buf-start) , whichever is longer.for automatic startup, the battery voltage should be present before v cc . if the controller attempts to bring the output into regulation without the battery voltagepresent, the fault latch trips. the controller remains shut down until the fault latch is cleared by toggling shdn or cycling the v cc power supply below 0.5v. if the v cc voltage drops below 4.25v, the controller assumes that there is not enough supply voltage tomake valid decisions and could also result in the stored boot vids being corrupted. as such, the max17009 immediately stops switching (dh_ and dl_ pulled low), latches off, and discharges the outputs using the inter- nal 10 switches from csl_ to gnd. see figure 6. t vrc ak nbv buf start boot time nbv buf (_ ) _ = () 7 143 t v mv s smps start boot () / = () 1 12 34 5 6 8 dc_in v ddio v core_ v nbv_buf svc/svd gnds2 (vdd_plane_strap) pwrgd pgd_in reset_l shdn 20 s 20 s 10 s 7 bus idle serial mode 2-bit boot vid blank high impedance figure 6. startup sequence downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller ______________________________________________________________________________________ 31 notes: 1) the relationship between dc_in and v ddio is not guaranteed. it is possible to have v ddio powered when dc_in is not powered, and it is possible tohave dc_in power-up before v ddio powers up. 2) as the v ddio power rail comes within specification, vdd_plane_strap becomes valid and svc and svdare driven to the boot vid value by the processor. the system guarantees that v ddio is in specification and svc and svd are driven to the boot vid valuefor at least 10? prior to shdn being asserted to the max17009. 3) after shdn is asserted, the max17009 samples and latches the vdd_plane_strap level at itsgnds2 pin when ref reaches the refok thresh- old, and ramps up the voltage-plane outputs to the level indicated by the 2-bit boot vid. the boot vid is stored in the max17009 for use when pgd_in deasserts. the max17009 soft-starts the output rails to limit inrush current from the dc_in rail. 4) the max17009 asserts pwrgd. after pwrgd is asserted and all system-wide voltage planes andfree-running clocks are within specification, then the system asserts pgd_in. 5) the processor holds the 2-bit boot vid for at least 10? after pgd_in is asserted. 6) the processor issues the set vid command through svi. 7) the max17009 transitions the voltage planes to the set vid. the set vid may be greater than, or lessthan the boot vid voltage. 8) the chipset enforces a 1ms delay between pgd_in assertion and reset_l deassertion. pwrgd the max17009 features internal power-good fault com-parators for each phase. the outputs of these individ- ual power-good fault comparators are logically ored to drive the gate of the open-drain pwrgd output transis- tor. each phase? power-good fault comparator has an upper threshold of +200mv (typ) and a lower threshold of -300mv (typ). pwrgd goes low if the output of either phase exceeds its respective thresholds. pwrgd is forced low during the startup sequence up to20? after both smps internal dacs reach the boot vid. the 2-bit boot vid is stored when pwrgd goes high during the startup sequence. pwrgd is immediately forced low when shdn goes low. pwrgd is blanked high impedance while either of theinternal smps dacs are slewing during a vid transition, plus an additional 20? after the dac transition is com- pleted. for downward vid transitions, the upper thresh- old of the power-good fault comparators remains blanked until the output reaches regulation again. pwrgd goes low for a minimum of 20? when pgd_in goes low, and stays low until 20? after both smps internal dacs reach the boot vid. pgd_in after the smps outputs reach the boot voltage, themax17009 switches over to the serial-interface mode when pgd_in goes high. anytime during normal opera- tion, a high-to-low transition on pgd_in causes the max17009 to slew all three internal dacs back to the stored boot vids. pwrgd goes low for a minimum of 20? when pgd_in goes low, and stays low until 20? after the smps outputs are within the pwrgd thresh- olds. the svc and svd inputs are disabled during the time that pgd_in is low. the serial interface is reen- abled when pgd_in goes high again. in debug mode ( pro = open), the function of the svc and svd inputs depend on the pgd_in level. ifpgd_in is low, the svc and svd inputs are used as 2- bit inputs to set the three internal dac voltages. see table 3. if pgd_in is high, the max17009 switches over to serial-interface mode. a high-to-low transition on pgd_in causes the max17009 to slew all three internal dacs back to the stored boot vids and revert to the 2-bit vid mode. see figure 7. downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller 32 ______________________________________________________________________________________ shutdown when shdn goes low, the max17009 enters the low- power shutdown mode. pwrgd is pulled low immedi-ately, and the smps output voltages ramp down at 1mv/?, while the nbv_buf output slews at a rate set by r time . at the end of the soft-shutdown sequence, dl_ is kept low, and the 10 switches from csl_ to gnd are enabled, holding the outputs low:slowly discharging the output capacitors by slewing the output over a long period of time keeps the average negative inductor current low (damped response), there- by eliminating the negative output-voltage excursion that occurs when the controller discharges the output quick-ly by permanently turning on the low-side mosfet (underdamped response). this eliminates the need for the schottky diode normally connected between the out- put and ground to clamp the negative output-voltage excursion. the max17009 shuts down completely?he drivers are disabled, the reference turns off, and the supply currents drop to about 1? (max)?0? after the controller reaches the 0v target. when a fault condi- tion?vervoltage or undervoltage?ccurs on one smps, the other smps and the nbv_buf immediately go through the soft-shutdown sequence. to clear the fault latch and reactivate the controller, toggle shdn or cycle v cc power below 0.5v. soft-shutdown for the nb regulator is determined by theparticular nb regulator? shutdown behavior. in the typ- ical application, the nb regulator? shdn pin or enable pin is toggled at the same time as the max17009?shdn pin. t vr c ak nbv buf shdn nbv buf time nbv buf (_ ) __ = () 7 143 t v mv s smps shdn out () / = () 1 svc/svd inputs disabled svc/svd (nbv_buf target) v nbv_buf pgd_in pwrgd v core0 (core0 target) (core1 target) v core1 2-bit boot vid note: max17009 is in skip mode. core0 is lightly loaded. core1 is heavily loaded. bus idle bus idle bus idle bus idle svc/svd (pro = open) 20 s 20 s blank high impedance figure 7. pgd_in timing figure downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller ______________________________________________________________________________________ 33 vrhot temperature comparator the max17009 features an independent comparatorwith an accurate threshold (v hot ) that tracks the ana- log supply voltage (v hot = 0.3 x v cc ). use a resistor- and thermistor-divider between v cc and gnd to gene- rate a voltage-regulator overtemperature monitor. placethe thermistor as close to the mosfets and inductors as possible. for combined-mode operations, the current-balance circuit balances the currents between phases. as such, the power loss and heat in each phase should be iden- tical, apart from the effects of placement and airflow over each phase. a single thermistor can be placed near either of the phases and still be effective. for separate mode operation, the load currents between phases may be very different. using two ?ogic-level thermistors (e.g., murata prf series positors) allows the same vrhot comparator to monitor the tempera- ture of both phases. figure 8 is the thrm configuration. fault protection (latched) p p r r o o selectable overvoltage protection and debug mode the max17009 features a tri-level pro pin that enables the overvoltage protection feature, or puts the max17009in debug mode. table 5 shows the pro -selectable options. debug mode is intended for applications wherethe serial interface is not properly functioning, and the output voltage needs to be adjusted to different levels. the dac voltage settings in debug mode further depend on the pgd_in level to switch between the 2-bit vid setting or the serial interface operation. output overvoltage protection the overvoltage-protection (ovp) circuit is designed toprotect the cpu against a shorted high-side mosfet by drawing high current and blowing the battery fuse. the max17009 continuously monitors the output for an overvoltage fault. the controller detects an ovp fault if the output voltage exceeds the set vid dac voltage by more than 300mv. the ovp threshold tracks the vid dac voltage except during a downward vid transition. during a downward vid transition, the ovp threshold is set at 1.80v (min), until the output reaches regulation, when the ovp threshold is reset back to 300mv above the vid setting. when the ovp circuit detects an overvoltage fault, it immediately forces the external low-side driver high on the faulted side and initiates the soft-shutdown for the other smps and the nbv_buf. the synchronous-recti- fier mosfets of the faulted side are turned on with 100% duty, which rapidly discharges the output filter capacitor and forces the output low. if the condition that caused the overvoltage (such as a shorted high- side mosfet) persists, the battery fuse blows. toggle shdn or cycle the v cc power supply below 0.5v to clear the fault latch and reactivate the controller.when in combined mode, the synchronous-rectifier mosfets of both phases are turned on with 100% duty in response to an overvoltage fault. overvoltage protection can be disabled by setting pro to high or open. output undervoltage protection the output uvp function is similar to foldback currentlimiting, but employs a timer rather than a variable cur- rent limit. if the max17009 output voltage is 400mv below the target voltage, the controller activates the shutdown sequence for both smps and nbv_buf, and sets the fault latch. toggle shdn or cycle the v cc power supply below 0.5v to clear the fault latch andreactivate the controller. thrm r thrm r thrm thrm place r ntc next to the hottest power component. place r ptc1 and r ptc2 next to the respective phase's power component. r ptc1 v cc v cc gnd gnd max17009 max17009 r ntc r ptc2 figure 8. thrm configuration pro description v cc ovp disabled open debug mode, ovp disabled gnd ovp enabled table 5. pro settings downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller 34 ______________________________________________________________________________________ thermal-fault protection the max17009 features a thermal-fault protection cir-cuit. when the junction temperature rises above +160?, a thermal sensor sets the fault latch and shuts down, immediately forcing dh and dl low, without going through the soft-shutdown sequence. toggle shdn or cycle the v cc power supply below 0.5v to clear the fault latch and reactivate the controller afterthe junction temperature cools by 15?. mosfet gate drivers the dh and dl drivers are optimized for driving mode-rate-sized high-side and larger low-side power mosfets. this is consistent with the low duty factor seen in notebook applications where a large v in - v out differential exists. the high-side gate drivers (dh)source and sink 2.2a, and the low-side gate drivers (dl) source 2.7a and sink 8a. this ensures robust gate drive for high-current applications. the dh floating high-side mosfet drivers are powered by internal boost switch charge pumps at bst, while the dl syn- chronous-rectifier drivers are powered directly by the 5v bias supply (v dd ). adaptive dead-time circuits monitor the dl and dh dri-vers and prevent either fet from turning on until the other is fully off. the adaptive driver dead time allows operation without shoot-through with a wide range of mosfets, minimizing delays and maintaining efficiency. there must be a low-resistance, low-inductance path from the dl and dh drivers to the mosfet gates for the adaptive dead-time circuits to work properly; other- wise, the sense circuitry in the max17009 interprets the mosfet gates as ?ff?while charge actually remains. use very short, wide traces (50 mils to 100 mils wide if the mosfet is 1in from the driver). the internal pulldown transistor that drives dl low is robust, with a 0.25 (typ) on-resistance. this helps pre- vent dl from being pulled up due to capacitive cou-pling from the drain to the gate of the low-side mosfets when the inductor node (lx) quickly switch- es from ground to v in . applications with high input volt- ages and long inductive driver traces may requirerising lx edges that do not pull up the low-side mosfets?gate, causing shoot-through currents. the capacitive coupling between lx and dl created by the mosfet? gate-to-drain capacitance (c rss ), gate-to- source capacitance (c iss - c rss ), and additional board parasitics should not exceed the following mini-mum threshold: typically, adding a 4700pf between dl and powerground (c nl in figure 9), close to the low-side mosfets, greatly reduces coupling. do not exceed22nf of total gate capacitance to prevent excessive turn-off delays. alternatively, shoot-through currents can be caused by a combination of fast high-side mosfets and slow low- side mosfets. if the turn-off delay time of the low-side mosfet is too long, the high-side mosfets can turn on before the low-side mosfets have actually turned off. adding a resistor less than 5 in series with bst slows down the high-side mosfet turn-on time, elimi-nating the shoot-through currents without degrading the turn-off time (r bst in figure 9). slowing down the high-side mosfet also reduces the lx node rise time,thereby reducing emi and high-frequency coupling responsible for switching noise. vv c c gs th in rss iss () > ? ? ? ? ? ? bst dh lx (r bst )* input (v in ) c bst n h c byp l (r bst )* optional?he resistor lowers emi by decreasing the switching node rise time. (c nl )* optional?he capacitor reduces lx to dl capacitive coupling that can cause shoot-through currents. dl pgnd n l (c nl )* v dd figure 9. gate drive circuit downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller ______________________________________________________________________________________ 35 offset and transient-phase repeat (option) the +12.5mv offset and the transient-phase repeat fea-tures of the max17009 can be selectively enabled and disabled by the option pin setting. table 6 shows the option pin voltage levels and the features that are enabled. see the transient phase repeat section for a detailed description of the respective features. whenthe offset is enabled, setting the psi_l bit low disables the offset reducing power consumption in the low- power state. smps design procedure firmly establish the input voltage range and maximumload current before choosing a switching frequency and inductor operating point (ripple-current ratio). the primary design trade-off lies in choosing a good switch- ing frequency and inductor operating point, and the fol- lowing four factors dictate the rest of the design: input voltage range: the maximum value (v in(max) ) must accommodate the worst-case high acadapter voltage. the minimum value (v in(min) ) must account for the lowest input voltage afterdrops due to connectors, fuses, and battery selec- tor switches. if there is a choice at all, lower input voltages result in better efficiency. maximum load current: there are two values to consider. the peak load current (i load(max) ) deter- mines the instantaneous component stresses and fil-tering requirements, and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. the continuous load cur- rent (i load ) determines the thermal stresses and thus drives the selection of input capacitors,mosfets, and other critical heat-contributing com- ponents. modern notebook cpus generally exhibit i load = i load(max) x 80%. for multiphase systems, each phase supports afraction of the load, depending on the current bal- ancing. when properly balanced, the load current is evenly distributed among each phase: where ph is the total number of active phases. switching frequency: this choice determines the basic trade-off between size and efficiency. theoptimal frequency is largely a function of maximum input voltage, due to mosfet switching losses that are proportional to frequency and v in 2 . the opti- mum frequency is also a moving target, due torapid improvements in mosfet technology that are making higher frequencies more practical. when selecting a switching frequency, the mini- mum on-time at the highest input voltage and low- est output voltage must be greater than the 185ns (max) minimum on-time specification in the electrical characteristics table: v out(min) / v in(max) x t sw > t onmin a good rule is to choose a minimum on-time of atleast 200ns. when in pulse-skipping operation skip_ = gnd, the minimum on-time must take into consideration the time needed for proper skip-mode operation. the on-time for a skip pulse must be greater than the 185ns (max) minimum on-time specification in the electrical characteristics table: inductor operating point: this choice provides trade-offs between size vs. efficiency and transientresponse vs. output noise. low inductor values pro- vide better transient response and smaller physical size, but also result in lower efficiency and higher output noise due to increased ripple current. the minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduc- tion (where the inductor current just touches zero with every cycle at maximum load). inductor values lower than this grant no further size-reduction bene- fit. the optimum operating point is usually found between 20% and 50% ripple current. inductor selection by design, the amd mobile serial vid applicationshould regard each of the max17009 smpss as inde- pendent, single-phase regulators. the switching fre- quency and operating point (% ripple current or lir) determine the inductor value as follows: t lv rv v onmin idle sense in max out min () () () i i load phase load ph () = option offset enabled transient-phase repeat enabled v cc 0 0 open 0 1 ref 1 0 gnd 1 1 table 6. option pin settings downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller 36 ______________________________________________________________________________________ where i load(max) is the maximum current per phase, and f sw is the switching frequency per phase. find a low-loss inductor having the lowest possible dcresistance that fits in the allotted dimensions. if using a swinging inductor (where the inductance decreases lin- early with increasing current), evaluate the lir with properly scaled inductance values. for the selected inductance value, the actual peak-to-peak inductor rip- ple current ( ? i inductor ) is defined by: ferrite cores are often the best choice, although pow-dered iron is inexpensive and can work well at 200khz. the core must be large enough not to saturate at the peak inductor current (i peak ): peak-inductor current limit (ilim) the max17009 overcurrent protection employs a peakcurrent-sensing algorithm that uses either current- sense resistors or the inductor? dcr as the current- sense element (see the current sense section). since the controller limits the peak inductor current, the maxi-mum average load current is less than the peak cur- rent-limit threshold by an amount equal to half the inductor ripple current. therefore, the maximum load capability is a function of the current-sense resistance, inductor value, switching frequency, and input-to-out- put voltage difference. when combined with the output undervoltage-protection circuit, the system is effectively protected against excessive overload conditions. the peak current-limit threshold is set by voltage differ- ence between ilim and ref using an external resistor- divider: v cs(pk) = v csp _ - v csn _ = 0.05 x (v ref - v ilim ) i limit(pk) = v cs(pk) / r sense where r sense is the resistance value of the current- sense element (inductors?dcr or current-sense resis-tor), and i limit(pk) is the desired peak current limit (per phase). the peak current-limit threshold voltage-adjust-ment range is from 10mv to 50mv. output-capacitor selection the output filter capacitor must have low-enough esrto meet output ripple and load-transient requirements. in cpu v core converters and other applications where the output is subject to large-load transients, the outputcapacitor? size typically depends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance: in non-cpu applications, the output capacitor? size often depends on how much esr is needed to maintain an acceptable level of output ripple voltage. the output ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capaci- tor? esr. when operating multiphase systems out-of- phase, the peak inductor currents of each phase are staggered, resulting in lower output-ripple voltage (v ripple ) by reducing the total inductor ripple current. for nonoverlapping, multiphase operation (v in v out ), the maximum esr to meet the output-ripple-voltagerequirement is: where f sw is the switching frequency per phase. the actual capacitance value required relates to the physi-cal size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor selection is usually limited by esr and volt- age rating rather than by capacitance value (this is true of polymer types). the capacitance value required is determined primarily by the output transient-response requirements. low inductor values allow the inductor current to slew faster, replenishing charge removed from or added to the out- put filter capacitors by a sudden load step. therefore, the amount of output soar when the load is removed is a function of the output voltage and inductor value. the minimum output capacitance required to prevent over- shoot (v soar ) due to stored inductor energy can be calculated as: c il vv out load max out soar () () 2 2 r vf l vv v v esr in sw in out out ripple () ? ? ? ? ? ? ? ? rr v i esr pcb step load max + () () i i i peak load max ph inductor = ? ? ? ? ? ? + ? ? ? ? ? ? () 2 i vvv vf l inductor out in out in sw = () l vv f i lir v v in out sw load max out in = ? ? ? ? ? ? ? ? ? ? ? ? () downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller ______________________________________________________________________________________ 37 when using low-capacity ceramic-filter capacitors,capacitor size is usually determined by the capacity needed to prevent v soar from causing problems during load transients. generally, once enough capacitance isadded to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem. input-capacitor selection the input capacitor must meet the ripple-currentrequirement (i rms ) imposed by the switching currents. for a dual, 180 interleaved controller, the out-of-phase operation reduces the rms input ripple current, effec- tively lowering the input capacitance requirements. when both outputs operate with a duty cycle less than 50% (v in > 2 x v out ), the rms input-ripple current is defined by the following equation:where i in is the average input current: in combined mode (gnds2 = v ddio ) with both phases active, the input rms current simplifies to:for most applications, nontantalum chemistries (ceramic, aluminum, or os-con) are preferred due to their resis- tance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input. if the max17009 is operated as the second stage of a two-stage power-conversion system, tantalum input capacitors are acceptable. in either configuration, choose an input capacitor that exhibits less than 10? temperature rise at the rms input current for optimal circuit longevity. voltage positioning and loop compensation voltage positioning dynamically lowers the output volt-age in response to the load current, reducing the out- put capacitance and processor? power-dissipation requirements. the controller uses two transconduc- tance amplifiers to set the transient and dc output-volt- age droop (figure 3). the transient-compensation (trc) amplifier determines how quickly the max17009 responds to the load transient. the fbdc_ amplifier adjusts the steady-state regulation voltage as a func- tion of the load. this adjustability allows flexibility in the selected current-sense resistor value or inductor dcr,and allows smaller current-sense resistance to be used, reducing the overall power dissipated. steady-state voltage positioning connect a resistor (r fbdc_ ) between fbdc_ and the remote-sense point to set the steady-state dc droop(load line) based on the required voltage-positioning slope (r droopdc ): r fbdc_ = r droopdc / (r sense_ x g m(fbdc_) ) where r droopdc is the desired steady-state droop, g m(fbdc_) is typically 1ms as defined in the electrical characteristics table, and r sense_ is the value of the current-sense resistor that is used to provide the(csp_, csn_) current-sense voltage. when the inductors?dcr is used as the current-sense element (r sense = r dcr ), the inductor dcr circuit should include an ntc thermistor to cancel the temper-ature dependence of the inductor dcr, maintaining a constant voltage-positioning slope. transient droop connect a resistor (r fbac_ ) between fbac_ and the remote-sense point to set the dc transient ac droop(load-line) based on the required voltage-positioning slope (r droopac ): r fbac_ = r droopac / (r sense_ x g m(fbac_) ) where r droopac is the desired steady-state droop, g m(fbac_) is typically 1ms as defined in the electrical characteristics table, and r sense_ is the value of the current-sense resistor that is used to provide the(csp_, csn_) current-sense voltage. when the inductors?dcr is used as the current-sense element (r sense = r dcr ), the inductor dcr circuit should include an ntc thermistor to cancel the temper-ature dependence of the inductor dcr, maintaining a constant voltage-positioning slope. power-mosfet selection most of the following mosfet guidelines focus on thechallenge of obtaining high load-current capability when using high-voltage (> 20v) ac adapters. low- current applications usually require less attention. the high-side mosfet (n h ) must be able to dissipate the resistive losses plus the switching losses at bothv in(min) and v in(max) . calculate both these sums. ideally, the losses at v in(min) should be roughly equal to losses at v in(max) , with lower losses in between. if the losses at v in(min) are significantly higher than the losses at v in(max) , consider increasing the size of n h (reducing r ds(on) but with higher c gate ). conversely, if the losses at v in(max) are significantly higher than the losses at ii v v v v rms out out in out in = ? ? ? ? ? ? ? ? ? ? ? ? 1 2 i v v i v v i in out in out out in out = ? ? ? ? ? ? + ? ? ? ? ? ? 1 1 2 2 i v v ii i v v ii i rms out in out out in out in out out in = ? ? ? ? ? ? () + ? ? ? ? ? ? () 1 11 2 22 downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller 38 ______________________________________________________________________________________ v in(min) , consider reducing the size of n h (increasing r ds(on) to lower c gate ). if v in does not vary over a wide range, the minimum power dissipation occurswhere the resistive losses equal the switching losses. choose a low-side mosfet that has the lowest possible on-resistance (r ds(on) ), comes in a moderate-sized package (i.e., one or two 8-pin sos, dpak, or d 2 pak), and is reasonably priced. make sure that the dl gatedriver can supply sufficient current to support the gate charge and the current injected into the parasitic gate- to-drain capacitor caused by the high-side mosfet turning on; otherwise, cross-conduction problems may occur (see the mosfet gate drivers section). mosfet power dissipation worst-case conduction losses occur at the duty-factorextremes. for the high-side mosfet (n h ), the worst- case power dissipation due to resistance occurs at theminimum input voltage: where i load is the per-phase current. generally, a small high-side mosfet is desired toreduce switching losses at high input voltages. however, the r ds(on) required to stay within package power dissipation often limits how small the mosfetcan be. again, the optimum occurs when the switching losses equal the conduction (r ds(on) ) losses. high- side switching losses do not usually become an issueuntil the input is greater than approximately 15v. calculating the power dissipation in high-side mosfet (n h ) due to switching losses is difficult since it must allow for difficult quantifying factors that influence theturn-on and turn-off times. these factors include the internal gate resistance, gate charge, threshold volt- age, source inductance, and pcb layout characteris- tics. the following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on n h : where c rss is the reverse transfer capacitance of n h and i gate is the peak gate-drive source/sink current (1a typ), and i load is the per-phase current. switching losses in the high-side mosfet can becomean insidious heat problem when maximum ac adapter voltages are applied, due to the squared term in the c x v in 2 x f sw switching-loss equation. if the high-side mosfet chosen for adequate r ds(on) at low-battery voltages becomes extraordinarily hot when biased fromv in(max) , consider choosing another mosfet with lower parasitic capacitance.for the low-side mosfet (n l ), the worst-case power dissipation always occurs at maximum input voltage:the worst case for mosfet power dissipation occurs under heavy overloads that are greater than i load(max) but are not quite high enough to exceed the current limit and cause the fault latch to trip. to pro-tect against this possibility, you can ?verdesign?the circuit to tolerate: where i peak(max) is the maximum valley current allowed by the current-limit circuit, including thresholdtolerance and on-resistance variation. the mosfets must have a good-size heatsink to handle the overload power dissipation. choose a schottky diode (d l ) with a forward voltage low enough to prevent the low-side mosfet bodydiode from turning on during the dead time. as a gen- eral rule, select a diode with a dc current rating equal to 1/3 the load current per phase. this diode is optional and can be removed if efficiency is not critical. boost capacitors the boost capacitors (c bst ) must be selected large enough to handle the gate-charging requirements ofthe high-side mosfets. typically, 0.1? ceramic capacitors work well for low-power applications driving medium-sized mosfets. however, high-current appli- cations driving large, high-side mosfets require boost capacitors larger than 0.1?. for these applications, select the boost capacitors to avoid discharging the capacitor more than 200mv while charging the high- side mosfets?gates: c nq mv bst gate = 200 ii i i i lir load max peak max inductor peak max load max () () () () = = ? ? ? ? ? ? 2 2 pd nl sistive v v i r out in max load total ds on (re ) () () = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 2 pd nhswitching v cf i i in max rss sw gate load () () = () ? ? ? ? ? ? 2 pd nh sistive v v ir out in load ds on (re ) () = ? ? ? ? ? ? 2 downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller ______________________________________________________________________________________ 39 where n is the number of high-side mosfets used forone regulator, and q gate is the gate charge specified in the mosfet? data sheet. for example, assume (2)irf7811w n-channel mosfets are used on the high side. according to the manufacturer? data sheet, a sin- gle irf7811w has a maximum gate charge of 24nc (v gs = 5v). using the above equation, the required boost capacitance would be:selecting the closest standard value, this example requires a 0.22? ceramic capacitor. svi applications information i 2 c-bus-compatible interface the max17009 is a receive-only device. the 2-wire ser-ial bus (pins svc and svd) is designed to attach on a low-voltage, i 2 c-like bus. in the amd mobile applica- tion, the cpu directly drives the bus at a speed of3.4mhz. the cpu has a push-pull output driving to the v ddio voltage level. external pullup resistors may be required during the initial power-up sequence beforethe cpu? push-pull drivers are active. refer to amd for specific implementation. when not used in the specific amd application, the ser- ial interface can be driven to as high as 2.5v, and oper- ate at the lower speeds (100khz, 400khz, or 1.7mhz). at lower clock speeds, external pullup resistors can be used for open-drain outputs. connect both svc and svd lines to v ddio through individual pullup resistors. calculate the required value of the pullup resistorsusing: where t r is the rise time, and should be less than 10% of the clock period. c bus is the total capacitance on the bus. the max17009 is compatible with the standard svi inter-face protocol as defined in the following subsections. bus not busy the svi bus is not busy when both data and clock linesremain high. data transfers can be initiated only when the bus is not busy. start data transfer (s) starting from an idle bus state (both svc and svd arehigh), a high to low transition of the data (svd) line while the clock (svc) is high determines a start condition. all commands must be preceded by a start condition. stop data transfer (p) a low to high transition of the sda line while theclock (svc) is high determines a stop condition. all operations must be ended with a stop condition. figure 10 shows the svi bus start, stop, and data change conditions slave address after generating a start condition, the bus mastertransmits the slave address consisting of a 7-bit device code (110xxxx) for the max17009. since the max17009 is a write-only device, the eighth bit of the slave address is zero. the max17009 monitors the bus for its corresponding slave address continuously. it generates an acknowledge bit if the slave address was true and it is not in a programming mode. svd data valid the state of the data line represents valid data when,after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low peri- od of the clock signal. there is one clock pulse per bit of data. r t pullup r c bus c nc mv f bst = = 224 200 024 . svc svd start condition s stop condition p data line stable data valid change of data allowed figure 10. svi bus start, stop, and data change conditions downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller 40 ______________________________________________________________________________________ acknowledge each receiving device, when addressed, is obliged togenerate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse that is associated with this acknowledge bit. the device that acknowledges has to pull down the svd line during the acknowledge clock pulse so the svd line is stable low during the high period of the acknowledge-related clock pulse. setup and hold times must be taken into account. see figure 11. figure 12 shows the svi bus data transfer summary. command byte a complete command consists of a start condition(s) followed by the max17009? slave address and a data phase, followed by a stop condition (p). smps applications information duty-cycle limits minimum input voltage the minimum input operating voltage (dropout voltage)is restricted by stability requirements, not the minimum off-time (t off(min) ). the max17009 does not include slope compensation, so the controller becomes unsta-ble with duty cycles greater than 50% per phase: v in(min) 2 x v out(max) however, the controller can briefly operate with dutycycles over 50% during heavy load transients. svc from master data output by max17009 data output by master clk1 start condition s 1 clk2 2 clk8 8 clk9 9 acknowledge clock pulse acknowledge not acknowledge d7 d6 d0 figure 11. svi bus acknowledge set dac and psi_l slave address s p st a r t st o p ac k ac k figure 12. svi bus data transfer summary downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller ______________________________________________________________________________________ 41 maximum input voltage the max17009 controller has a minimum on-time,which determines the maximum input operating voltage that maintains the selected switching frequency. with higher input voltages, each pulse delivers more energy than the output is sourcing to the load. at the beginning of each cycle, if the output voltage is still above the feedback threshold voltage, the controller does not trig- ger an on-time pulse, resulting in pulse-skipping opera- tion. this allows the controller to maintain regulation above the maximum input voltage, but forces the con- troller to effectively operate with a lower switching fre- quency. this results in an input threshold voltage at which the controller begins to skip pulses (v in(skip) ): where f sw is the per-phase switching frequency set by the osc resistor, and t onmin is 185ns (max) minus the driver? turn-on delay (dl low to dh high). for the besthigh-voltage performance, use the slowest switching frequency setting (100khz per phase, r osc = 432k ). pcb layout guidelines careful pcb layout is critical to achieve low switchinglosses and clean, stable operation. the switching power stage requires particular attention (figure 13). if possible, mount all the power components on the top side of the board with their ground terminals flush against one another, and mount the controller and ana- log components on the bottom layer so the internal ground layers shield the analog components from any noise generated by the power components. follow these guidelines for good pcb layout: keep the high-current paths short, especially at the ground terminals. this is essential for stable, jitter-free operation. connect all analog grounds to a separate solid cop- per plane, then connect the analog ground to thegnd pins of the controller. the following sensitive components connect to analog ground: v cc , v ddio , and ref bypass capacitors, remote-sense andgnds bypass capacitors, and the resistive connec- tions (ilim, osc, time). keep the power traces and load connections short. this is essential for high efficiency. the use of thickcopper pcbs (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. correctly routing pcb traces is a difficult task that must be approached in terms of fractions of centimeters, where a single m of excess trace resistance causes a measurableefficiency penalty. connections for current limiting (csp_, csn_) and voltage positioning (fbs, gnds) must be madeusing kelvin-sense connections to guarantee the current-sense accuracy. place current-sense filter capacitors and voltage-positioning filter capacitors as close to the ic as possible. route high-speed switching nodes and driver traces away from sensitive analog areas (ref, v cc , fbac, fbdc, etc.). make all pin-strap control inputconnections ( shdn , pgd_in, option) to analog ground or v cc rather than power ground or v dd . route the high-speed serial-interface signals (svc, svd) in parallel, keeping the trace lengths identical.keep the svc and svd away from the high-current switching paths. vv ft in skip out sw onmin () = ? ? ? ? ? ? 1 bits description 6:4 always 110b 3 x = don? care 2 v dac2 , if set, then the following data byte contains the vid for v dac2 ; bit 2 is ignored in combined mode (gnds2 = v ddio ) 1 v dac1 , if set, then the following data byte contains the vid for v dac1 in separate mode, and the unified vdd in combined mode 0 v dac_nb , if set then the following data byte contains the vid for v dac_nb table 7. svi send byte address description bits description 7 psi_l: power-save indicator:? 0 means the processor is at an optimal load and the regulator(s) can enter power-savingmode. offset is disabled if previously enabled through the option pin. the max17009 enters 1-phase operation if in combined mode (gnds2 = h). ? 1 means the processor is at a high current- consumption state. offset is enabled ifpreviously enabled through the option pin. the max17009 returns to 2-phase operation if in combined mode (gnds2 = h). 6:0 svid[6:0] as defined in table 7. table 8. serial vid 8-bit data field encoding downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller 42 ______________________________________________________________________________________ keep the drivers close to the mosfet, with the gate-drive traces (dl, dh, lx, and bst) short andwide to minimize trace resistance and inductance. this is essential for high-power mosfets that require low-impedance gate drivers to avoid shoot- through currents. when trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to bemade longer than the discharge path. for example, it is better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low- side mosfet or between the inductor and the out- put filter capacitor. layout procedure 1) place the power components first, with ground ter- minals adjacent (low-side mosfet source, c in , c out , and dl anode). if possible, make all these connections on the top layer with wide, copper-filled areas. 2) mount the driver ic adjacent to the low-side mosfets. the dl gate traces must be short andwide (50 mils to 100 mils wide if the mosfet is 1in from the driver ic). 3) group the gate-drive components (bst capacitors, v dd bypass capacitor) together near the driver ic. 4) make the dc-dc controller ground connections as shown in the standard application circuit in figure2. this diagram can be viewed as having three sep- arate ground planes: input/output ground, where all the high-power components go; the power ground plane, where the pgnd pin, v dd bypass capacitor, and driver ic ground connection go; and the con-troller? analog ground plane where sensitive ana- log components, the master? gnd pin, and v cc bypass capacitor go. the controller? analogground plane (gnd) must meet the power ground plane (pgnd) only at a single point directly beneath the ic. the power ground plane should connect to the high-power output ground with a short, thick metal trace from pgnd to the source of the low-side mosfets (the middle of the star ground). 5) connect the output power planes (v core and sys- tem ground planes) directly to the output-filtercapacitor positive and negative terminals with multi- ple vias. place the entire dc-dc converter circuit as close to the cpu as is practical. figure 13 is a pcb layout example. split corecpu socket kelvin sense vias under the inductors for dcr sensing connect the exposed pad to analog gnd analogground (inner layer) inductor power ground inductor input v ddnb v core0 c out c out c in c in c vdd1 c ref c vdd2 c vcc c in c in c out c out v core1 figure 13. pcb layout example downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller ______________________________________________________________________________________ 43 chip information transistor count: 14,497process: bicmos max17009 thin qfn 5mm x 5mm top view 3536 34 33 1211 13 nbv_buf ref ilim osc time 14 pwrgd dl1gnd2 dl2 v dd1 bst1 lx1v dd2 bst2 12 csp1 4567 27 28 29 30 26 24 23 22 csn1 pgd_in v cc csp2csn2 gnds_nb shdn gnd1 3 25 37 option v ddio 3839 40 fbac1 fbdc1 gnds1 fbac2fbdc2 gnds2 pro 32 15 vrhot 31 16 17 18 19 20 dh2 svcsvd thrm lx2 8910 21 dh1 nbskp pin configuration downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller 44 ______________________________________________________________________________________ package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) qfn thin.eps downloaded from: http:///
max17009 amd mobile serial vid dual-phase fixed-frequency controller maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 45 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) downloaded from: http:///

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